From patchwork Wed Aug 21 00:18:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Pinski X-Patchwork-Id: 1974619 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=quicinc.com header.i=@quicinc.com header.a=rsa-sha256 header.s=qcppdkim1 header.b=PGUB65Ha; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4WpRmd1WZ0z1ydn for ; Wed, 21 Aug 2024 10:19:58 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2F7623870870 for ; Wed, 21 Aug 2024 00:19:56 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by sourceware.org (Postfix) with ESMTPS id 3D72A387086C for ; Wed, 21 Aug 2024 00:19:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3D72A387086C Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=quicinc.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 3D72A387086C Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1724199569; cv=none; b=C8G2tGTaxNmX+nukLG7G8ahijWHQsxYoWopanzD86Fqq3i0t2SA1BS9WTeGppG1K9RBHzeviRiVYl5zRghgXecogicB7kJLINHZDV+L8AqtD2YJvVxSOBoS+poUHiJW5YGpDUZF4TctY+p0XKXlPWz6tF04QPlrsl4Dqul9L7q8= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1724199569; c=relaxed/simple; bh=WHX1uvOIldP0BwOwVQZOd++oxQHjfOUyF3Lt9b7Dd2k=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=w1I0w0k95M/nSLqjvuYq7HANBDoupsL5QWTKWvpwTNlswpeXsgNnSEUoZCkDRSABeZNmRLHMgn6Q/aI8tdfvxhYPAAgto1IWOSymyxAhcsKv2D/pl9UyH3XUXKXLzHyubNQVhTY3oNrVHZWzikI3bWpAJ7nYxaeiVkDmA++9W1o= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 47KDZmZS005613 for ; Wed, 21 Aug 2024 00:19:00 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:message-id :mime-version:subject:to; s=qcppdkim1; bh=opHN1TSZDFbObQxDxja34e Bd/8WAb1UE1B9sp0pGALw=; b=PGUB65Ha1gz6GZ/TnZVpqjtUfB6pz08cHFf8Cb lgcmWyYWoA5BYuJ2oUea5JLL7ZwYkyMLq9dyvzx5J6yeNoHCEzPpSAkph6iqRpUI yzjeuM5xG6r0pX7LQEGUQ+H2edTUdIVjhkaTAGqjuuP6C9caxNJQc4eaIWOetE8T zS65ARmQbRsjNVkkJUkUz2g1UBLrEea+IcEab1E7ZZ+TN94l7tsSZH3RkvIZ6gFR QCIJC209fW4VEmBONwW2lqt5a31XLpB2Ykx5c9KeNAl10qz/rabmBlc/DdM3vECe 6JnsqSxshiqhNf3aS/Oy5HNVhL9+rBoFgeclxe85YZuMOW5w== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 414v5c9c1y-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 21 Aug 2024 00:18:59 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47L0IxCl015193 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 21 Aug 2024 00:18:59 GMT Received: from hu-apinski-lv.qualcomm.com (10.49.16.6) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 20 Aug 2024 17:18:58 -0700 From: Andrew Pinski To: CC: Andrew Pinski Subject: [PATCH v2] aarch64: Implement popcountti2 pattern [PR113042] Date: Tue, 20 Aug 2024 17:18:38 -0700 Message-ID: <20240821001838.3698348-1-quic_apinski@quicinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: cqlkKYjnDl1gljq34UNMsQeK4fL_2_Qy X-Proofpoint-ORIG-GUID: cqlkKYjnDl1gljq34UNMsQeK4fL_2_Qy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-20_18,2024-08-19_03,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=0 spamscore=0 adultscore=0 lowpriorityscore=0 bulkscore=0 impostorscore=0 phishscore=0 priorityscore=1501 clxscore=1015 malwarescore=0 mlxlogscore=852 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408210000 X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org When CSSC is not enabled, 128bit popcount can be implemented just via the vector (v16qi) cnt instruction followed by a reduction, like how the 64bit one is currently implemented instead of splitting into 2 64bit popcount. Changes since v1: * v2: Make operand 0 be DImode instead of TImode and simplify. Build and tested for aarch64-linux-gnu. PR target/113042 gcc/ChangeLog: * config/aarch64/aarch64.md (popcountti2): New define_expand. gcc/testsuite/ChangeLog: * gcc.target/aarch64/popcnt10.c: New test. * gcc.target/aarch64/popcnt9.c: New test. Signed-off-by: Andrew Pinski --- gcc/config/aarch64/aarch64.md | 13 +++++++++++ gcc/testsuite/gcc.target/aarch64/popcnt10.c | 25 +++++++++++++++++++++ gcc/testsuite/gcc.target/aarch64/popcnt9.c | 25 +++++++++++++++++++++ 3 files changed, 63 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/popcnt10.c create mode 100644 gcc/testsuite/gcc.target/aarch64/popcnt9.c diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 12dcc16529a..c54b29cd64b 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -5378,6 +5378,19 @@ (define_expand "popcount2" } }) +(define_expand "popcountti2" + [(match_operand:DI 0 "register_operand") + (match_operand:TI 1 "register_operand")] + "TARGET_SIMD && !TARGET_CSSC" +{ + rtx v = gen_reg_rtx (V16QImode); + rtx v1 = gen_reg_rtx (V16QImode); + emit_move_insn (v, gen_lowpart (V16QImode, operands[1])); + emit_insn (gen_popcountv16qi2 (v1, v)); + emit_insn (gen_aarch64_zero_extenddi_reduc_plus_v16qi (operands[0], v1)); + DONE; +}) + (define_insn "clrsb2" [(set (match_operand:GPI 0 "register_operand" "=r") (clrsb:GPI (match_operand:GPI 1 "register_operand" "r")))] diff --git a/gcc/testsuite/gcc.target/aarch64/popcnt10.c b/gcc/testsuite/gcc.target/aarch64/popcnt10.c new file mode 100644 index 00000000000..4d01fc67022 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/popcnt10.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-optimized" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +/* PR target/113042 */ + +#pragma GCC target "+cssc" + +/* +** h128: +** ldp x([0-9]+), x([0-9]+), \[x0\] +** cnt x([0-9]+), x([0-9]+) +** cnt x([0-9]+), x([0-9]+) +** add w0, w([0-9]+), w([0-9]+) +** ret +*/ + + +unsigned h128 (const unsigned __int128 *a) { + return __builtin_popcountg (a[0]); +} + +/* popcount with CSSC should be split into 2 sections. */ +/* { dg-final { scan-tree-dump-not "POPCOUNT " "optimized" } } */ +/* { dg-final { scan-tree-dump-times " __builtin_popcount" 2 "optimized" } } */ + diff --git a/gcc/testsuite/gcc.target/aarch64/popcnt9.c b/gcc/testsuite/gcc.target/aarch64/popcnt9.c new file mode 100644 index 00000000000..c778fc7f420 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/popcnt9.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-optimized" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +/* PR target/113042 */ + +#pragma GCC target "+nocssc" + +/* +** h128: +** ldr q([0-9]+), \[x0\] +** cnt v([0-9]+).16b, v\1.16b +** addv b([0-9]+), v\2.16b +** fmov w0, s\3 +** ret +*/ + + +unsigned h128 (const unsigned __int128 *a) { + return __builtin_popcountg (a[0]); +} + +/* There should be only one POPCOUNT. */ +/* { dg-final { scan-tree-dump-times "POPCOUNT " 1 "optimized" } } */ +/* { dg-final { scan-tree-dump-not " __builtin_popcount" "optimized" } } */ +