| Message ID | 20240819081442.1955204-1-shiyulong@iscas.ac.cn |
|---|---|
| State | New |
| Headers | show |
| Series | RISC-V: Bugfix for Duplicate entries for -mtune in --target-help[Bug 116347] | expand |
On 8/19/24 2:14 AM, shiyulong@iscas.ac.cn wrote: > From: yulong <shiyulong@iscas.ac.cn> > > This patch try to fix a bug[116347]. I change the name of the micro-arch, > because I think micro-arch and core have the same name that caused the error. > > gcc/ChangeLog: > > * config/riscv/riscv-cores.def (RISCV_TUNE): Rename. > (RISCV_CORE): Ditto. Conceptually tuning means things like costs and scheduler model while core defines what instructions can be used. So why are core entries showing up under known arguments for the -mtune option? Jeff
在 2024/8/25 23:38, Jeff Law 写道: > > > On 8/19/24 2:14 AM, shiyulong@iscas.ac.cn wrote: >> From: yulong <shiyulong@iscas.ac.cn> >> >> This patch try to fix a bug[116347]. I change the name of the >> micro-arch, >> because I think micro-arch and core have the same name that caused >> the error. >> >> gcc/ChangeLog: >> >> * config/riscv/riscv-cores.def (RISCV_TUNE): Rename. >> (RISCV_CORE): Ditto. > Conceptually tuning means things like costs and scheduler model while > core defines what instructions can be used. So why are core entries > showing up under known arguments for the -mtune option? > > Jeff In the current definition, different cores need to be configured with corresponding tuning in `riscv-cores.def`, so we can reuse the core name in '-mtune' option. BR, Jiawei
On 8/25/24 8:03 PM, Jiawei wrote: > > 在 2024/8/25 23:38, Jeff Law 写道: >> >> >> On 8/19/24 2:14 AM, shiyulong@iscas.ac.cn wrote: >>> From: yulong <shiyulong@iscas.ac.cn> >>> >>> This patch try to fix a bug[116347]. I change the name of the micro- >>> arch, >>> because I think micro-arch and core have the same name that caused >>> the error. >>> >>> gcc/ChangeLog: >>> >>> * config/riscv/riscv-cores.def (RISCV_TUNE): Rename. >>> (RISCV_CORE): Ditto. >> Conceptually tuning means things like costs and scheduler model while >> core defines what instructions can be used. So why are core entries >> showing up under known arguments for the -mtune option? >> >> Jeff > > In the current definition, different cores need to be configured with > corresponding tuning in `riscv-cores.def`, so we can reuse the core name > in '-mtune' option. I don't think that's what we really want from a behavior standpoint. Something seems wrong. jeff
On Sat, 07 Sep 2024 10:32:07 PDT (-0700), jeffreyalaw@gmail.com wrote: > > > On 8/25/24 8:03 PM, Jiawei wrote: >> >> 在 2024/8/25 23:38, Jeff Law 写道: >>> >>> >>> On 8/19/24 2:14 AM, shiyulong@iscas.ac.cn wrote: >>>> From: yulong <shiyulong@iscas.ac.cn> >>>> >>>> This patch try to fix a bug[116347]. I change the name of the micro- >>>> arch, >>>> because I think micro-arch and core have the same name that caused >>>> the error. >>>> >>>> gcc/ChangeLog: >>>> >>>> * config/riscv/riscv-cores.def (RISCV_TUNE): Rename. >>>> (RISCV_CORE): Ditto. >>> Conceptually tuning means things like costs and scheduler model while >>> core defines what instructions can be used. So why are core entries >>> showing up under known arguments for the -mtune option? >>> >>> Jeff >> >> In the current definition, different cores need to be configured with >> corresponding tuning in `riscv-cores.def`, so we can reuse the core name >> in '-mtune' option. > I don't think that's what we really want from a behavior standpoint. > Something seems wrong. Ya, sorry I didn't get around to looking at this -- it's still on the TODO list, I guess I just keep getting discracted with other stuff...
diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def index 2f5efe3be86..e9fc63625fe 100644 --- a/gcc/config/riscv/riscv-cores.def +++ b/gcc/config/riscv/riscv-cores.def @@ -39,8 +39,8 @@ RISCV_TUNE("sifive-5-series", generic, rocket_tune_info) RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info) RISCV_TUNE("sifive-p400-series", sifive_p400, sifive_p400_tune_info) RISCV_TUNE("sifive-p600-series", sifive_p600, sifive_p600_tune_info) -RISCV_TUNE("thead-c906", generic, thead_c906_tune_info) -RISCV_TUNE("xiangshan-nanhu", xiangshan, xiangshan_nanhu_tune_info) +RISCV_TUNE("thead-c906-series", generic, thead_c906_tune_info) +RISCV_TUNE("xiangshan-nanhu-series", xiangshan, xiangshan_nanhu_tune_info) RISCV_TUNE("generic-ooo", generic_ooo, generic_ooo_tune_info) RISCV_TUNE("size", generic, optimize_size_tune_info) @@ -90,10 +90,10 @@ RISCV_CORE("sifive-p670", "rv64imafdcv_za64rs_zic64b_zicbom_zicbop_zicboz_" RISCV_CORE("thead-c906", "rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_" "xtheadcondmov_xtheadfmemidx_xtheadmac_" "xtheadmemidx_xtheadmempair_xtheadsync", - "thead-c906") + "thead-c906-series") RISCV_CORE("xiangshan-nanhu", "rv64imafdc_zba_zbb_zbc_zbs_" "zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_" "svinval_zicbom_zicboz", - "xiangshan-nanhu") + "xiangshan-nanhu-series") #undef RISCV_CORE
From: yulong <shiyulong@iscas.ac.cn> This patch try to fix a bug[116347]. I change the name of the micro-arch, because I think micro-arch and core have the same name that caused the error. gcc/ChangeLog: * config/riscv/riscv-cores.def (RISCV_TUNE): Rename. (RISCV_CORE): Ditto. --- gcc/config/riscv/riscv-cores.def | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)