From patchwork Mon Aug 19 02:04:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1973633 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=k6ybcLtV; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4WnGCJ0LrQz1yXZ for ; Mon, 19 Aug 2024 12:05:30 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B080E384DEFC for ; Mon, 19 Aug 2024 02:05:28 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by sourceware.org (Postfix) with ESMTPS id EB7D1386182F for ; Mon, 19 Aug 2024 02:04:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EB7D1386182F Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org EB7D1386182F Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=198.175.65.13 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1724033099; cv=none; b=TaKw2S6A7+bzg3mRP9PsFxsCfUe8MtLYsdgCGoXynGyZDgLd1BrM6cfPS5dQBEYcH/sLyvnYoAOjrQEcC8blTRSjKXEEXz8byrTKcnOdjwd2oN7EKmtWeTZeMSedntcqjDCkJwbKdwpteTkWA67mmI5BBDhdKPLw4QTwnLRpMAs= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1724033099; c=relaxed/simple; bh=pyzsaTGZ/eraJvVZWew0Ai7ttUSbL5s5OYrkrrKtJoY=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=TtU63MFkaSVlIHQiSzmsEwrBvEAaBJ0L3Vny7ajgJxoouItBxDAO3Nq59liIJF3zpN48elVi6+sRt5r+a6M4I3GDh+RIo+aJ7VCjrdjMEljHjM6ZBSmNxd4YeO/QtHLgg5q20jfx4THm1bY2N2EYbLREmlTDP5EkcskLdd6siL8= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724033097; x=1755569097; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=pyzsaTGZ/eraJvVZWew0Ai7ttUSbL5s5OYrkrrKtJoY=; b=k6ybcLtVVEfke0yt3UvKZRIbVD+/ujDAXevjKQxkMxlYt46WDOD30lk7 SFjidcZCxXmnLoUvfQYLfxR2LOjyM2cz6w1BQdkAiVfL8q6LgQ2b1xR1G GBScbRrwHQv0fbXhAY29i6NPBBkJjHyDkJUHLz56dZdRBalTrBJXZQEga 9j7c/RvKrFUUVgIdfKFU+trMga7jUwEzw6NyX5pDCvfTHt7noIOVS3QDU gQZ6ZteUk4QyKKRPCx70UpIDxVLGr3gKCWC0mTaTFI5KV0X0yrMAoFYvO 3N5WRe/ayt1BqgJhJKsZfxOqUd5U7vXqcHI0RkXhgFMGEwOt1jZW8q1LZ A==; X-CSE-ConnectionGUID: bNlM5pY6TT+MfNNNOYZcnQ== X-CSE-MsgGUID: BGkRJkzoRpKcbvwWKLNOFg== X-IronPort-AV: E=McAfee;i="6700,10204,11168"; a="33406197" X-IronPort-AV: E=Sophos;i="6.10,158,1719903600"; d="scan'208";a="33406197" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2024 19:04:55 -0700 X-CSE-ConnectionGUID: 6q7XhcdDR8W3qbeSop5EDw== X-CSE-MsgGUID: 89D9rsKzRGKCylgdBf7nlQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,158,1719903600"; d="scan'208";a="60504535" Received: from panli.sh.intel.com ([10.239.154.73]) by orviesa006.jf.intel.com with ESMTP; 18 Aug 2024 19:04:53 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2 Date: Mon, 19 Aug 2024 10:04:29 +0800 Message-ID: <20240819020430.1041509-1-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li This patch would like to add test cases for the unsigned scalar quad and oct .SAT_TRUNC form 2. Aka: Form 2: #define DEF_SAT_U_TRUC_FMT_2(NT, WT) \ NT __attribute__((noinline)) \ sat_u_truc_##WT##_to_##NT##_fmt_2 (WT x) \ { \ WT max = (WT)(NT)-1; \ return x > max ? (NT) max : (NT)x; \ } QUAD: DEF_SAT_U_TRUC_FMT_2 (uint16_t, uint64_t) DEF_SAT_U_TRUC_FMT_2 (uint8_t, uint32_t) OCT: DEF_SAT_U_TRUC_FMT_2 (uint8_t, uint64_t) The below test is passed for this patch. * The rv64gcv regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_u_trunc-10.c: New test. * gcc.target/riscv/sat_u_trunc-11.c: New test. * gcc.target/riscv/sat_u_trunc-12.c: New test. * gcc.target/riscv/sat_u_trunc-run-10.c: New test. * gcc.target/riscv/sat_u_trunc-run-11.c: New test. * gcc.target/riscv/sat_u_trunc-run-12.c: New test. Signed-off-by: Pan Li Signed-off-by: Pan Li --- .../gcc.target/riscv/sat_u_trunc-10.c | 17 ++++++++++++++++ .../gcc.target/riscv/sat_u_trunc-11.c | 17 ++++++++++++++++ .../gcc.target/riscv/sat_u_trunc-12.c | 20 +++++++++++++++++++ .../gcc.target/riscv/sat_u_trunc-run-10.c | 16 +++++++++++++++ .../gcc.target/riscv/sat_u_trunc-run-11.c | 16 +++++++++++++++ .../gcc.target/riscv/sat_u_trunc-run-12.c | 16 +++++++++++++++ 6 files changed, 102 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-11.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-12.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-11.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-12.c diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-10.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-10.c new file mode 100644 index 00000000000..7dfc740c54f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-10.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_truc_uint32_t_to_uint8_t_fmt_2: +** sltiu\s+[atx][0-9]+,\s*a0,\s*255 +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff +** ret +*/ +DEF_SAT_U_TRUC_FMT_2(uint8_t, uint32_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-11.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-11.c new file mode 100644 index 00000000000..c50ae96f47d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-11.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_truc_uint64_t_to_uint8_t_fmt_2: +** sltiu\s+[atx][0-9]+,\s*a0,\s*255 +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff +** ret +*/ +DEF_SAT_U_TRUC_FMT_2(uint8_t, uint64_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-12.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-12.c new file mode 100644 index 00000000000..61331cee6fa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-12.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_truc_uint64_t_to_uint16_t_fmt_2: +** li\s+[atx][0-9]+,\s*65536 +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 +** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** slli\s+a0,\s*a0,\s*48 +** srli\s+a0,\s*a0,\s*48 +** ret +*/ +DEF_SAT_U_TRUC_FMT_2(uint16_t, uint64_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-10.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-10.c new file mode 100644 index 00000000000..4bc9303e457 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-10.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint8_t +#define T2 uint32_t + +DEF_SAT_U_TRUC_FMT_2_WRAP(T1, T2) + +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define RUN_UNARY(x) RUN_SAT_U_TRUC_FMT_2_WRAP(T1, T2, x) + +#include "scalar_sat_unary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-11.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-11.c new file mode 100644 index 00000000000..a2afdb9ab22 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-11.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint8_t +#define T2 uint64_t + +DEF_SAT_U_TRUC_FMT_2_WRAP(T1, T2) + +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define RUN_UNARY(x) RUN_SAT_U_TRUC_FMT_2_WRAP(T1, T2, x) + +#include "scalar_sat_unary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-12.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-12.c new file mode 100644 index 00000000000..699485cf139 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-12.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint16_t +#define T2 uint64_t + +DEF_SAT_U_TRUC_FMT_2_WRAP(T1, T2) + +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define RUN_UNARY(x) RUN_SAT_U_TRUC_FMT_2_WRAP(T1, T2, x) + +#include "scalar_sat_unary.h"