[07/22] AVX10.2 ymm rounding: Support vcvtqq2p{s, d, h} and vcvttpd2{, u}{dq, qq} intrins

Message ID	20240814090159.422097-8-haochen.jiang@intel.com
State	New
Headers	show Return-Path: <gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org> DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 98B95385DDC4 From: Haochen Jiang <haochen.jiang@intel.com> To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com, ubizjak@gmail.com, "Hu, Lin1" <lin1.hu@intel.com> Subject: [PATCH 07/22] AVX10.2 ymm rounding: Support vcvtqq2p{s, d, h} and vcvttpd2{, u}{dq, qq} intrins Date: Wed, 14 Aug 2024 17:01:44 +0800 Message-Id: <20240814090159.422097-8-haochen.jiang@intel.com> In-Reply-To: <20240814090159.422097-1-haochen.jiang@intel.com> References: <20240814090159.422097-1-haochen.jiang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: list Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org
Series	Support AVX10.2 ymm rounding \| expand [00/22] Support AVX10.2 ymm rounding [01/22] AVX10.2 ymm rounding: Support vadd{s, d, h} and vcmp{s, d, h} intrins [02/22] AVX10.2 ymm rounding: Support vcvtdq2p{s, h} and vcvtpd2p{s, h} intrins [03/22] AVX10.2 ymm rounding: Support vcvtpd2{, u}{dq, qq} intrins [04/22] AVX10.2 ymm rounding: Support vcvtph2p{s, d, sx} and vcvtph2{, u}{dq, qq} intrins [05/22] AVX10.2 ymm rounding: Support vcvtph2{, u}w and vcvtps2p{d, hx} intrins [06/22] AVX10.2 ymm rounding: Support vcvtps2{, u}{dq, qq} intrins [07/22] AVX10.2 ymm rounding: Support vcvtqq2p{s, d, h} and vcvttpd2{, u}{dq, qq} intrins [08/22] AVX10.2 ymm rounding: Support vcvttph2{, u}{dq, qq, w} intrins [09/22] AVX10.2 ymm rounding: Support vcvttps2{, u}{dq, qq} and vcvtu{dq, qq}2p{s, d, h} intrins [10/22] AVX10.2 ymm rounding: Support vcvt{, u}w2ph and vdivp{s, d, h} intrins [11/22] AVX10.2 ymm rounding: Support vfc{madd, mul}cph, vfixupimmp{s, d} intrins [12/22] AVX10.2 ymm rounding: Support vfmadd{132, 231, 213}p{s, d, h} intrins [13/22] AVX10.2 ymm rounding: Support vfmaddcph and vfmaddsub{132, 231, 213}p{s, d, h} intrins [14/22] AVX10.2 ymm rounding: Support vfm{sub, subadd}{132, 231, 213}p{s, d, h} intrins [15/22] AVX10.2 ymm rounding: Support vfmulcph and vfnmadd{132, 231, 213}p{s, d, h} intrins [16/22] AVX10.2 ymm rounding: Support vfnmsub{132, 231, 213}p{s, d, h} intrins [17/22] AVX10.2 ymm rounding: Support vgetexpp{s, d, h} and vgetmantp{s, d, h} intrins [18/22] AVX10.2 ymm rounding: Support v{max, min}p{s, d, h} intrins [19/22] AVX10.2 ymm rounding: Support vmulp{s, d, h} and vrangep{s, d} intrins [20/22] AVX10.2 ymm rounding: Support vreducep{s, d, h} and vrndscalep{s, d, h} intrins [21/22] AVX10.2 ymm rounding: Support vscalefp{s,d,h} intrins [22/22] AVX10.2 ymm rounding: Support vsqrtp{s, d, h} and vsubp{s, d, h} intrins

diff --git a/gcc/config/i386/avx10_2roundingintrin.h b/gcc/config/i386/avx10_2roundingintrin.h index fca10a6b586..25efd9d7b96 100644 --- a/gcc/config/i386/avx10_2roundingintrin.h +++ b/gcc/config/i386/avx10_2roundingintrin.h @@ -1003,6 +1003,244 @@ _mm256_maskz_cvt_roundps_epu64 (__mmask8 __U, __m128 __A, const int __R) (__mmask8) __U, __R); } + +extern __inline __m256d +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_cvt_roundepi64_pd (__m256i __A, const int __R) +{ + return (__m256d) __builtin_ia32_cvtqq2pd256_mask_round ((__v4di) __A, + (__v4df) + _mm256_setzero_pd (), + (__mmask8) -1, + __R); +} + +extern __inline __m256d +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_cvt_roundepi64_pd (__m256d __W, __mmask8 __U, __m256i __A, + const int __R) +{ + return (__m256d) __builtin_ia32_cvtqq2pd256_mask_round ((__v4di) __A, + (__v4df) __W, + (__mmask8) __U, + __R); +} + +extern __inline __m256d +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_cvt_roundepi64_pd (__mmask8 __U, __m256i __A, const int __R) +{ + return (__m256d) __builtin_ia32_cvtqq2pd256_mask_round ((__v4di) __A, + (__v4df) + _mm256_setzero_pd (), + (__mmask8) __U, + __R); +} + +extern __inline __m128h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_cvt_roundepi64_ph (__m256i __A, const int __R) +{ + return (__m128h) __builtin_ia32_vcvtqq2ph256_mask_round ((__v4di) __A, + (__v8hf) + _mm_setzero_ph (), + (__mmask8) -1, + __R); +} + +extern __inline __m128h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_cvt_roundepi64_ph (__m128h __W, __mmask8 __U, __m256i __A, + const int __R) +{ + return (__m128h) __builtin_ia32_vcvtqq2ph256_mask_round ((__v4di) __A, + (__v8hf) __W, + (__mmask8) __U, + __R); +} + +extern __inline __m128h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_cvt_roundepi64_ph (__mmask8 __U, __m256i __A, const int __R) +{ + return (__m128h) __builtin_ia32_vcvtqq2ph256_mask_round ((__v4di) __A, + (__v8hf) + _mm_setzero_ph (), + (__mmask8) __U, + __R); +} + +extern __inline __m128 +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_cvt_roundepi64_ps (__m256i __A, const int __R) +{ + return (__m128) __builtin_ia32_cvtqq2ps256_mask_round ((__v4di) __A, + (__v4sf) + _mm_setzero_ps (), + (__mmask8) -1, + __R); +} + +extern __inline __m128 +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_cvt_roundepi64_ps (__m128 __W, __mmask8 __U, __m256i __A, + const int __R) +{ + return (__m128) __builtin_ia32_cvtqq2ps256_mask_round ((__v4di) __A, + (__v4sf) __W, + (__mmask8) __U, + __R); +} + +extern __inline __m128 +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_cvt_roundepi64_ps (__mmask8 __U, __m256i __A, const int __R) +{ + return (__m128) __builtin_ia32_cvtqq2ps256_mask_round ((__v4di) __A, + (__v4sf) + _mm_setzero_ps (), + (__mmask8) __U, + __R); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_cvtt_roundpd_epi32 (__m256d __A, const int __R) +{ + return + (__m128i) __builtin_ia32_cvttpd2dq256_mask_round ((__v4df) __A, + (__v4si) + _mm_undefined_si128 (), + (__mmask8) -1, + __R); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_cvtt_roundpd_epi32 (__m128i __W, __mmask8 __U, __m256d __A, + const int __R) +{ + return (__m128i) __builtin_ia32_cvttpd2dq256_mask_round ((__v4df) __A, + (__v4si) __W, + (__mmask8) __U, + __R); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_cvtt_roundpd_epi32 (__mmask8 __U, __m256d __A, const int __R) +{ + return (__m128i) __builtin_ia32_cvttpd2dq256_mask_round ((__v4df) __A, + (__v4si) + _mm_setzero_si128 (), + (__mmask8) __U, + __R); +} + +extern __inline __m256i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_cvtt_roundpd_epi64 (__m256d __A, const int __R) +{ + return + (__m256i) __builtin_ia32_cvttpd2qq256_mask_round ((__v4df) __A, + (__v4di) + _mm256_setzero_si256 (), + (__mmask8) -1, + __R); +} + +extern __inline __m256i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_cvtt_roundpd_epi64 (__m256i __W, __mmask8 __U, __m256d __A, + const int __R) +{ + return (__m256i) __builtin_ia32_cvttpd2qq256_mask_round ((__v4df) __A, + (__v4di) __W, + (__mmask8) __U, + __R); +} + +extern __inline __m256i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_cvtt_roundpd_epi64 (__mmask8 __U, __m256d __A, const int __R) +{ + return + (__m256i) __builtin_ia32_cvttpd2qq256_mask_round ((__v4df) __A, + (__v4di) + _mm256_setzero_si256 (), + (__mmask8) __U, + __R); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_cvtt_roundpd_epu32 (__m256d __A, const int __R) +{ + return + (__m128i) __builtin_ia32_cvttpd2udq256_mask_round ((__v4df) __A, + (__v4si) + _mm_undefined_si128 (), + (__mmask8) -1, + __R); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_cvtt_roundpd_epu32 (__m128i __W, __mmask8 __U, __m256d __A, + const int __R) +{ + return (__m128i) __builtin_ia32_cvttpd2udq256_mask_round ((__v4df) __A, + (__v4si) __W, + (__mmask8) __U, + __R); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_cvtt_roundpd_epu32 (__mmask8 __U, __m256d __A, const int __R) +{ + return + (__m128i) __builtin_ia32_cvttpd2udq256_mask_round ((__v4df) __A, + (__v4si) + _mm_setzero_si128 (), + (__mmask8) __U, + __R); +} + +extern __inline __m256i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_cvtt_roundpd_epu64 (__m256d __A, const int __R) +{ + return + (__m256i) __builtin_ia32_cvttpd2uqq256_mask_round ((__v4df) __A, + (__v4di) \ + _mm256_setzero_si256 (), + (__mmask8) -1, + __R); +} + +extern __inline __m256i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_cvtt_roundpd_epu64 (__m256i __W, __mmask8 __U, __m256d __A, + const int __R) +{ + return (__m256i) __builtin_ia32_cvttpd2uqq256_mask_round ((__v4df) __A, + (__v4di) __W, + (__mmask8) __U, + __R); +} + +extern __inline __m256i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_cvtt_roundpd_epu64 (__mmask8 __U, __m256d __A, const int __R) +{ + return + (__m256i) __builtin_ia32_cvttpd2uqq256_mask_round ((__v4df) __A, + (__v4di) + _mm256_setzero_si256 (), + (__mmask8) __U, + __R); +} #else #define _mm256_add_round_pd(A, B, R) \ ((__m256d) __builtin_ia32_addpd256_mask_round ((__v4df) (A), \ @@ -1585,6 +1823,158 @@ _mm256_maskz_cvt_roundps_epu64 (__mmask8 __U, __m128 __A, const int __R) (_mm256_setzero_si256 ()), \ (__mmask8) (U), \ (R))) + +#define _mm256_cvt_roundepi64_pd(A, R) \ + ((__m256d) __builtin_ia32_cvtqq2pd256_mask_round ((__v4di) (A), \ + (__v4df) \ + (_mm256_setzero_pd ()), \ + (__mmask8) (-1), \ + (R))) + +#define _mm256_mask_cvt_roundepi64_pd(W, U, A, R) \ + ((__m256d) __builtin_ia32_cvtqq2pd256_mask_round ((__v4di) (A), \ + (__v4df) (W), \ + (__mmask8) (U), \ + (R))) + +#define _mm256_maskz_cvt_roundepi64_pd(U, A, R) \ + ((__m256d) __builtin_ia32_cvtqq2pd256_mask_round ((__v4di) (A), \ + (__v4df) \ + (_mm256_setzero_pd ()), \ + (__mmask8) (U), \ + (R))) + +#define _mm256_cvt_roundepi64_ph(A, R) \ + ((__m128h) __builtin_ia32_vcvtqq2ph256_mask_round ((__v4di) (A), \ + (__v8hf) \ + (_mm_setzero_ph ()), \ + (__mmask8) (-1), \ + (R))) + +#define _mm256_mask_cvt_roundepi64_ph(W, U, A, R) \ + ((__m128h) __builtin_ia32_vcvtqq2ph256_mask_round ((__v4di) (A), \ + (__v8hf) (W), \ + (__mmask8) (U), \ + (R))) + +#define _mm256_maskz_cvt_roundepi64_ph(U, A, R) \ + ((__m128h) __builtin_ia32_vcvtqq2ph256_mask_round ((__v4di) (A), \ + (__v8hf) \ + (_mm_setzero_ph ()), \ + (__mmask8) (U), \ + (R))) + +#define _mm256_cvt_roundepi64_ps(A, R) \ + ((__m128) __builtin_ia32_cvtqq2ps256_mask_round ((__v4di) (A), \ + (__v4sf) \ + (_mm_setzero_ps ()), \ + (__mmask8) (-1), \ + (R))) + +#define _mm256_mask_cvt_roundepi64_ps(W, U, A, R) \ + ((__m128) __builtin_ia32_cvtqq2ps256_mask_round ((__v4di) (A), \ + (__v4sf) (W), \ + (__mmask8) (U), \ + (R))) + +#define _mm256_maskz_cvt_roundepi64_ps(U, A, R) \ + ((__m128) __builtin_ia32_cvtqq2ps256_mask_round ((__v4di) (A), \ + (__v4sf) \ + (_mm_setzero_ps ()), \ + (__mmask8) (U), \ + (R))) + +#define _mm256_cvtt_roundpd_epi32(A, R) \ + ((__m128i) __builtin_ia32_cvttpd2dq256_mask_round ((__v4df) (A), \ + (__v4si) \ + (_mm_undefined_si128 ()), \ + (__mmask8) (-1), \ + (R))) + +#define _mm256_mask_cvtt_roundpd_epi32(W, U, A, R) \ + ((__m128i) __builtin_ia32_cvttpd2dq256_mask_round ((__v4df) (A), \ + (__v4si) (W), \ + (__mmask8) (U), \ + (R))) + +#define _mm256_maskz_cvtt_roundpd_epi32(U, A, R) \ + ((__m128i) __builtin_ia32_cvttpd2dq256_mask_round ((__v4df) (A), \ + (__v4si) \ + (_mm_setzero_si128 ()), \ + (__mmask8) (U), \ + (R))) + +#define _mm256_cvtt_roundpd_epi64(A, R) \ + ((__m256i) \ + __builtin_ia32_cvttpd2qq256_mask_round ((__v4df) (A), \ + (__v4di) \ + (_mm256_setzero_si256 ()), \ + (__mmask8) (-1), \ + (R))) + +#define _mm256_mask_cvtt_roundpd_epi64(W, U, A, R) \ + ((__m256i) __builtin_ia32_cvttpd2qq256_mask_round ((__v4df) (A), \ + (__v4di) (W), \ + (__mmask8) (U), \ + (R))) + +#define _mm256_maskz_cvtt_roundpd_epi64(U, A, R) \ + ((__m256i) \ + __builtin_ia32_cvttpd2qq256_mask_round ((__v4df) (A), \ + (__v4di) \ + (_mm256_setzero_si256 ()), \ + (__mmask8) (U), \ + (R))) + +#define _mm256_cvtt_roundpd_epu32(A, R) \ + ((__m128i) \ + __builtin_ia32_cvttpd2udq256_mask_round ((__v4df) (A), \ + (__v4si) \ + (_mm_undefined_si128 ()), \ + (__mmask8) (-1), \ + (R))) + +#define _mm256_mask_cvtt_roundpd_epu32(W, U, A, R) \ + ((__m128i) __builtin_ia32_cvttpd2udq256_mask_round ((__v4df) (A), \ + (__v4si) (W), \ + (__mmask8) (U), \ + (R))) + +#define _mm256_maskz_cvtt_roundpd_epu32(U, A, R) \ + ((__m128i) __builtin_ia32_cvttpd2udq256_mask_round ((__v4df) (A), \ + (__v4si) \ + (_mm_setzero_si128 ()), \ + (__mmask8) (U), \ + (R))) +#define _mm256_cvtt_roundpd_epu64(A, R) \ + ((__m256i) \ + __builtin_ia32_cvttpd2uqq256_mask_round ((__v4df) (A), \ + (__v4di) \ + (_mm256_setzero_si256 ()), \ + (__mmask8) (-1), \ + (R))) + +#define _mm256_mask_cvtt_roundpd_epu64(W, U, A, R) \ + ((__m256i) __builtin_ia32_cvttpd2uqq256_mask_round ((__v4df) (A), \ + (__v4di) (W), \ + (__mmask8) (U), \ + (R))) + +#define _mm256_maskz_cvtt_roundpd_epu64(U, A, R) \ + ((__m256i) \ + __builtin_ia32_cvttpd2uqq256_mask_round ((__v4df) (A), \ + (__v4di) \ + (_mm256_setzero_si256 ()), \ + (__mmask8) (U), \ + (R))) + +#define _mm256_cvtt_roundph_epi32(A, R) \ + ((__m256i) \ + __builtin_ia32_vcvttph2dq256_mask_round ((__v8hf) (A), \ + (__v8si) \ + (_mm256_setzero_si256 ()), \ + (__mmask8) (-1), \ + (R))) #endif #ifdef __DISABLE_AVX10_2_256__ diff --git a/gcc/config/i386/i386-builtin-types.def b/gcc/config/i386/i386-builtin-types.def index 111d6e7651c..adbc6d22f4c 100644 --- a/gcc/config/i386/i386-builtin-types.def +++ b/gcc/config/i386/i386-builtin-types.def @@ -1436,3 +1436,6 @@ DEF_FUNCTION_TYPE (V4DF, V4SF, V4DF, UQI, INT) DEF_FUNCTION_TYPE (V8HF, V8SF, V8HF, UQI, INT) DEF_FUNCTION_TYPE (V8SI, V8SF, V8SI, UQI, INT) DEF_FUNCTION_TYPE (V4DI, V4SF, V4DI, UQI, INT) +DEF_FUNCTION_TYPE (V4DF, V4DI, V4DF, UQI, INT) +DEF_FUNCTION_TYPE (V8HF, V4DI, V8HF, UQI, INT) +DEF_FUNCTION_TYPE (V4SF, V4DI, V4SF, UQI, INT) diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index b623be7b742..8e03ecfc6d7 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -3348,6 +3348,13 @@ BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx_fix_notruncv8sfv8si_mask_ro BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512dq_cvtps2qqv4di_mask_round, "__builtin_ia32_cvtps2qq256_mask_round", IX86_BUILTIN_VCVTPS2QQ256_MASK_ROUND, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_UQI_INT) BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fixuns_notruncv8sfv8si_mask_round, "__builtin_ia32_cvtps2udq256_mask_round", IX86_BUILTIN_VCVTPS2UDQ256_MASK_ROUND, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_UQI_INT) BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512dq_cvtps2uqqv4di_mask_round, "__builtin_ia32_cvtps2uqq256_mask_round", IX86_BUILTIN_VCVTPS2UQQ256_MASK_ROUND, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_UQI_INT) +BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_floatv4div4df2_mask_round, "__builtin_ia32_cvtqq2pd256_mask_round", IX86_BUILTIN_VCVTQQ2PD256_MASK_ROUND, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_UQI_INT) +BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512fp16_vcvtqq2ph_v4di_mask_round, "__builtin_ia32_vcvtqq2ph256_mask_round", IX86_BUILTIN_VCVTQQ2PH256_MASK_ROUND, UNKNOWN, (int) V8HF_FTYPE_V4DI_V8HF_UQI_INT) +BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_floatv4div4sf2_mask_round, "__builtin_ia32_cvtqq2ps256_mask_round", IX86_BUILTIN_VCVTQQ2PS256_MASK_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_UQI_INT) +BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_unspec_fix_truncv4dfv4si2_mask_round, "__builtin_ia32_cvttpd2dq256_mask_round", IX86_BUILTIN_VCVTTPD2DQ256_MASK_ROUND, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_UQI_INT) +BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_unspec_fix_truncv4dfv4di2_mask_round, "__builtin_ia32_cvttpd2qq256_mask_round", IX86_BUILTIN_VCVTTPD2QQ256_MASK_ROUND, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_UQI_INT) +BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_unspec_fixuns_truncv4dfv4si2_mask_round, "__builtin_ia32_cvttpd2udq256_mask_round", IX86_BUILTIN_VCVTTPD2UDQ256_MASK_ROUND, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_UQI_INT) +BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_unspec_fixuns_truncv4dfv4di2_mask_round, "__builtin_ia32_cvttpd2uqq256_mask_round", IX86_BUILTIN_VCVTTPD2UQQ256_MASK_ROUND, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_UQI_INT) BDESC_END (ROUND_ARGS, MULTI_ARG) diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index 5ea260b89b9..8c2a7c7e33d 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -12469,6 +12469,7 @@ ix86_expand_round_builtin (const struct builtin_description *d, case V8SF_FTYPE_V8HF_V8SF_UQI_INT: case V8SI_FTYPE_V8SF_V8SI_UQI_INT: case V8SI_FTYPE_V8HF_V8SI_UQI_INT: + case V4DF_FTYPE_V4DI_V4DF_UQI_INT: case V4DF_FTYPE_V4SF_V4DF_UQI_INT: case V4DF_FTYPE_V8HF_V4DF_UQI_INT: case V4DI_FTYPE_V8HF_V4DI_UQI_INT: @@ -12477,12 +12478,14 @@ ix86_expand_round_builtin (const struct builtin_description *d, case V2DF_FTYPE_V2DF_V2DF_V2DF_INT: case V4SI_FTYPE_V4DF_V4SI_UQI_INT: case V4SF_FTYPE_V4DF_V4SF_UQI_INT: + case V4SF_FTYPE_V4DI_V4SF_UQI_INT: case V4SF_FTYPE_V4SF_V4SF_V4SF_INT: case V8HF_FTYPE_V8DI_V8HF_UQI_INT: case V8HF_FTYPE_V8DF_V8HF_UQI_INT: case V8HF_FTYPE_V8SF_V8HF_UQI_INT: case V8HF_FTYPE_V8SI_V8HF_UQI_INT: case V8HF_FTYPE_V4DF_V8HF_UQI_INT: + case V8HF_FTYPE_V4DI_V8HF_UQI_INT: case V16HF_FTYPE_V16SF_V16HF_UHI_INT: case V8HF_FTYPE_V8HF_V8HF_V8HF_INT: nargs = 4; diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index ef852da7b3a..1353a51f0fb 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -7422,6 +7422,19 @@ (set_attr "prefix" "evex") (set_attr "mode" "<sseinsnmode>")]) +(define_expand "avx512fp16_vcvt<floatsuffix>qq2ph_v4di_mask_round" + [(match_operand:V8HF 0 "register_operand") + (any_float:V4HF (match_operand:V4DI 1 "register_operand")) + (match_operand:V8HF 2 "nonimm_or_0_operand") + (match_operand:QI 3 "register_operand") + (unspec [(match_operand:SI 4 "const_4_or_8_to_11_operand")] UNSPEC_EMBEDDED_ROUNDING)] + "TARGET_AVX10_2_256" +{ + emit_insn (gen_avx512fp16_vcvt<floatsuffix>qq2ph_v4di_mask_round_1 ( + operands[0], operands[1], operands[2], operands[3], CONST0_RTX (V4HFmode), operands[4])); + DONE; +}) + (define_expand "avx512fp16_vcvt<floatsuffix><sseintconvert>2ph_<mode>_mask" [(set (match_operand:V8HF 0 "register_operand" "=v") (vec_concat:V8HF @@ -7435,18 +7448,18 @@ "TARGET_AVX512FP16 && TARGET_AVX512VL" "operands[4] = CONST0_RTX (V4HFmode);") -(define_insn "*avx512fp16_vcvt<floatsuffix><sseintconvert>2ph_<mode>_mask" +(define_insn "avx512fp16_vcvt<floatsuffix><sseintconvert>2ph_<mode>_mask<round_name>_1" [(set (match_operand:V8HF 0 "register_operand" "=v") (vec_concat:V8HF (vec_merge:V4HF - (any_float:V4HF (match_operand:VI4_128_8_256 1 "vector_operand" "vm")) + (any_float:V4HF (match_operand:VI4_128_8_256 1 "<round_nimm_predicate>" "<round_constraint>")) (vec_select:V4HF (match_operand:V8HF 2 "nonimm_or_0_operand" "0C") (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)])) (match_operand:QI 3 "register_operand" "Yk")) (match_operand:V4HF 4 "const0_operand")))] - "TARGET_AVX512FP16 && TARGET_AVX512VL" - "vcvt<floatsuffix><sseintconvert>2ph<qq2phsuff>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" + "TARGET_AVX512FP16 && TARGET_AVX512VL && <round_mode_condition>" + "vcvt<floatsuffix><sseintconvert>2ph<round_qq2phsuff>\t{<round_op5>%1, %0%{%3%}%N2|%0%{%3%}%N2, %1<round_op5>}" [(set_attr "type" "ssecvt") (set_attr "prefix" "evex") (set_attr "mode" "<sseinsnmode>")]) @@ -8908,7 +8921,7 @@ [(set (match_operand:VF2_AVX512VL 0 "register_operand" "=v") (any_float:VF2_AVX512VL (match_operand:<sseintvecmode> 1 "nonimmediate_operand" "<round_constraint>")))] - "TARGET_AVX512DQ" + "TARGET_AVX512DQ && <round_mode_condition>" "vcvt<floatsuffix>qq2pd\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}" [(set_attr "type" "ssecvt") (set_attr "prefix" "evex") @@ -8923,7 +8936,7 @@ (any_float:<ssePSmode2> (match_operand:VI8_256_512 1 "nonimmediate_operand" "<round_constraint>")))] "TARGET_AVX512DQ && <round_mode_condition>" - "vcvt<floatsuffix>qq2ps<qq2pssuff>\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}" + "vcvt<floatsuffix>qq2ps<round_qq2pssuff>\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}" [(set_attr "type" "ssecvt") (set_attr "prefix" "evex") (set_attr "mode" "<sseinsnmode>")]) @@ -9381,12 +9394,13 @@ (set_attr "prefix" "evex") (set_attr "mode" "TI")]) -(define_insn "unspec_fix_truncv4dfv4si2<mask_name>" +(define_insn "unspec_fix_truncv4dfv4si2<mask_name><round_saeonly_name>" [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4DF 1 "nonimmediate_operand" "vm")] + (unspec:V4SI [(match_operand:V4DF 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")] UNSPEC_VCVTT))] - "TARGET_AVX || (TARGET_AVX512VL && TARGET_AVX512F)" - "vcvttpd2dq{y}\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}" + "TARGET_AVX && <mask_avx512vl_condition> + && (!<round_saeonly_applied> || TARGET_AVX10_2_256)" + "vcvttpd2dq<round_saeonly_suff>\t{<round_saeonly_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}" [(set_attr "type" "ssecvt") (set_attr "prefix" "maybe_evex") (set_attr "mode" "OI")]) @@ -9400,12 +9414,13 @@ (set_attr "prefix" "maybe_evex") (set_attr "mode" "OI")]) -(define_insn "unspec_fixuns_truncv4dfv4si2<mask_name>" +(define_insn "unspec_fixuns_truncv4dfv4si2<mask_name><round_saeonly_name>" [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4DF 1 "nonimmediate_operand" "vm")] + (unspec:V4SI [(match_operand:V4DF 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")] UNSPEC_VCVTTU))] - "TARGET_AVX512VL && TARGET_AVX512F" - "vcvttpd2udq{y}\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}" + "TARGET_AVX512VL && TARGET_AVX512F + && (!<round_saeonly_applied> || TARGET_AVX10_2_256)" + "vcvttpd2udq<round_saeonly_suff>\t{<round_saeonly_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}" [(set_attr "type" "ssecvt") (set_attr "prefix" "maybe_evex") (set_attr "mode" "OI")]) diff --git a/gcc/config/i386/subst.md b/gcc/config/i386/subst.md index 3d0979ba18a..3e75c234db6 100644 --- a/gcc/config/i386/subst.md +++ b/gcc/config/i386/subst.md @@ -199,6 +199,7 @@ (define_subst_attr "round_constraint" "round" "vm" "v") (define_subst_attr "round_suff" "round" "{y}" "") (define_subst_attr "round_qq2phsuff" "round" "<qq2phsuff>" "") +(define_subst_attr "round_qq2pssuff" "round" "<qq2pssuff>" "") (define_subst_attr "round_pd2udqsuff" "round" "<pd2udqsuff>" "") (define_subst_attr "bcst_round_constraint" "round" "vmBr" "v") (define_subst_attr "round_constraint2" "round" "m" "v") @@ -262,6 +263,7 @@ (define_subst_attr "round_saeonly_constraint2" "round_saeonly" "m" "v") (define_subst_attr "round_saeonly_nimm_predicate" "round_saeonly" "vector_operand" "register_operand") (define_subst_attr "round_saeonly_nimm_scalar_predicate" "round_saeonly" "nonimmediate_operand" "register_operand") +(define_subst_attr "round_saeonly_suff" "round_saeonly" "{y}" "") (define_subst_attr "round_saeonly_mode_condition" "round_saeonly" "1" "((<MODE>mode == V16SFmode || <MODE>mode == V8DFmode || <MODE>mode == V8DImode diff --git a/gcc/testsuite/gcc.target/i386/avx-1.c b/gcc/testsuite/gcc.target/i386/avx-1.c index f9424dedf40..a9e1d4f1fba 100644 --- a/gcc/testsuite/gcc.target/i386/avx-1.c +++ b/gcc/testsuite/gcc.target/i386/avx-1.c @@ -872,6 +872,13 @@ #define __builtin_ia32_cvtps2qq256_mask_round(A, B, C, D) __builtin_ia32_cvtps2qq256_mask_round(A, B, C, 8) #define __builtin_ia32_cvtps2udq256_mask_round(A, B, C, D) __builtin_ia32_cvtps2udq256_mask_round(A, B, C, 8) #define __builtin_ia32_cvtps2uqq256_mask_round(A, B, C, D) __builtin_ia32_cvtps2uqq256_mask_round(A, B, C, 8) +#define __builtin_ia32_cvtqq2pd256_mask_round(A, B, C, D) __builtin_ia32_cvtqq2pd256_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtqq2ph256_mask_round(A, B, C, D) __builtin_ia32_vcvtqq2ph256_mask_round(A, B, C, 8) +#define __builtin_ia32_cvtqq2ps256_mask_round(A, B, C, D) __builtin_ia32_cvtqq2ps256_mask_round(A, B, C, 8) +#define __builtin_ia32_cvttpd2dq256_mask_round(A, B, C, D) __builtin_ia32_cvttpd2dq256_mask_round(A, B, C, 8) +#define __builtin_ia32_cvttpd2qq256_mask_round(A, B, C, D) __builtin_ia32_cvttpd2qq256_mask_round(A, B, C, 8) +#define __builtin_ia32_cvttpd2udq256_mask_round(A, B, C, D) __builtin_ia32_cvttpd2udq256_mask_round(A, B, C, 8) +#define __builtin_ia32_cvttpd2uqq256_mask_round(A, B, C, D) __builtin_ia32_cvttpd2uqq256_mask_round(A, B, C, 8) #include <wmmintrin.h> #include <immintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-rounding-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-rounding-2.c new file mode 100644 index 00000000000..4675100d41f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_2-rounding-2.c @@ -0,0 +1,72 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx10.2" } */ +/* { dg-final { scan-assembler-times "vcvtqq2pd\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%ymm\[0-9\]+\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtqq2pd\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\n\]*%ymm\[0-9\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtqq2pd\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%ymm\[0-9\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtqq2phy\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtqq2ph\[ \\t\]+\{rn-sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtqq2ph\[ \\t\]+\{rz-sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtqq2ps\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%ymm\[0-9\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtqq2ps\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\n\]*%ymm\[0-9\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtqq2ps\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%ymm\[0-9\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2dq\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%ymm\[0-9\]+\[^\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2dq\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%ymm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2dq\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%ymm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2qq\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2qq\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2qq\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2udq\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%ymm\[0-9\]+\[^\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2udq\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%ymm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2udq\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%ymm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2uqq\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2uqq\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2uqq\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m128 hx; +volatile __m128i hxi; +volatile __m128h hxh; +volatile __m256 x; +volatile __m256d xd; +volatile __m256h xh; +volatile __m256i xi; +volatile __mmask8 m8; +volatile __mmask16 m16; +volatile __mmask32 m32; + +void extern +avx10_2_test_1 (void) +{ + xd = _mm256_cvt_roundepi64_pd (xi, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC); + xd = _mm256_mask_cvt_roundepi64_pd (xd, m8, xi, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC); + xd = _mm256_maskz_cvt_roundepi64_pd (m8, xi, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC); + + hxh = _mm256_cvt_roundepi64_ph (xi, 4); + hxh = _mm256_mask_cvt_roundepi64_ph (hxh, m8, xi, 8); + hxh = _mm256_maskz_cvt_roundepi64_ph (m8, xi, 11); + + hx = _mm256_cvt_roundepi64_ps (xi, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC); + hx = _mm256_mask_cvt_roundepi64_ps (hx, m8, xi, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC); + hx = _mm256_maskz_cvt_roundepi64_ps (m8, xi, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC); +} + +void extern +avx10_2_test_2 (void) +{ + hxi = _mm256_cvtt_roundpd_epi32 (xd, _MM_FROUND_NO_EXC); + hxi = _mm256_mask_cvtt_roundpd_epi32 (hxi, m8, xd, _MM_FROUND_NO_EXC); + hxi = _mm256_maskz_cvtt_roundpd_epi32 (m8, xd, _MM_FROUND_NO_EXC); + + xi = _mm256_cvtt_roundpd_epi64 (xd, _MM_FROUND_NO_EXC); + xi = _mm256_mask_cvtt_roundpd_epi64 (xi, m8, xd, _MM_FROUND_NO_EXC); + xi = _mm256_maskz_cvtt_roundpd_epi64 (m8, xd, _MM_FROUND_NO_EXC); + + hxi = _mm256_cvtt_roundpd_epu32 (xd, _MM_FROUND_NO_EXC); + hxi = _mm256_mask_cvtt_roundpd_epu32 (hxi, m8, xd, _MM_FROUND_NO_EXC); + hxi = _mm256_maskz_cvtt_roundpd_epu32 (m8, xd, _MM_FROUND_NO_EXC); + + xi = _mm256_cvtt_roundpd_epu64 (xd, _MM_FROUND_NO_EXC); + xi = _mm256_mask_cvtt_roundpd_epu64 (xi, m8, xd, _MM_FROUND_NO_EXC); + xi = _mm256_maskz_cvtt_roundpd_epu64 (m8, xd, _MM_FROUND_NO_EXC); +} diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c index 90547e480de..98e292faf32 100644 --- a/gcc/testsuite/gcc.target/i386/sse-13.c +++ b/gcc/testsuite/gcc.target/i386/sse-13.c @@ -879,5 +879,12 @@ #define __builtin_ia32_cvtps2qq256_mask_round(A, B, C, D) __builtin_ia32_cvtps2qq256_mask_round(A, B, C, 8) #define __builtin_ia32_cvtps2udq256_mask_round(A, B, C, D) __builtin_ia32_cvtps2udq256_mask_round(A, B, C, 8) #define __builtin_ia32_cvtps2uqq256_mask_round(A, B, C, D) __builtin_ia32_cvtps2uqq256_mask_round(A, B, C, 8) +#define __builtin_ia32_cvtqq2pd256_mask_round(A, B, C, D) __builtin_ia32_cvtqq2pd256_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtqq2ph256_mask_round(A, B, C, D) __builtin_ia32_vcvtqq2ph256_mask_round(A, B, C, 8) +#define __builtin_ia32_cvtqq2ps256_mask_round(A, B, C, D) __builtin_ia32_cvtqq2ps256_mask_round(A, B, C, 8) +#define __builtin_ia32_cvttpd2dq256_mask_round(A, B, C, D) __builtin_ia32_cvttpd2dq256_mask_round(A, B, C, 8) +#define __builtin_ia32_cvttpd2qq256_mask_round(A, B, C, D) __builtin_ia32_cvttpd2qq256_mask_round(A, B, C, 8) +#define __builtin_ia32_cvttpd2udq256_mask_round(A, B, C, D) __builtin_ia32_cvttpd2udq256_mask_round(A, B, C, 8) +#define __builtin_ia32_cvttpd2uqq256_mask_round(A, B, C, D) __builtin_ia32_cvttpd2uqq256_mask_round(A, B, C, 8) #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc/testsuite/gcc.target/i386/sse-14.c index 2d55185bffc..fcfdc87f856 100644 --- a/gcc/testsuite/gcc.target/i386/sse-14.c +++ b/gcc/testsuite/gcc.target/i386/sse-14.c @@ -1043,6 +1043,13 @@ test_1 (_mm256_cvt_roundps_epi32, __m256i, __m256, 9) test_1 (_mm256_cvt_roundps_epu32, __m256i, __m256, 9) test_1 (_mm256_cvt_roundps_epi64, __m256i, __m128, 8) test_1 (_mm256_cvt_roundps_epu64, __m256i, __m128, 8) +test_1 (_mm256_cvt_roundepi64_pd, __m256d, __m256i, 8) +test_1 (_mm256_cvt_roundepi64_ph, __m128h, __m256i, 8) +test_1 (_mm256_cvt_roundepi64_ps, __m128, __m256i, 8) +test_1 (_mm256_cvtt_roundpd_epi32, __m128i, __m256d, 8) +test_1 (_mm256_cvtt_roundpd_epi64, __m256i, __m256d, 8) +test_1 (_mm256_cvtt_roundpd_epu32, __m128i, __m256d, 8) +test_1 (_mm256_cvtt_roundpd_epu64, __m256i, __m256d, 8) test_2 (_mm256_add_round_pd, __m256d, __m256d, __m256d, 9) test_2 (_mm256_add_round_ph, __m256h, __m256h, __m256h, 8) test_2 (_mm256_add_round_ps, __m256, __m256, __m256, 9) @@ -1069,6 +1076,13 @@ test_2 (_mm256_maskz_cvt_roundps_epi32, __m256i, __mmask8, __m256, 9) test_2 (_mm256_maskz_cvt_roundps_epu32, __m256i, __mmask8, __m256, 9) test_2 (_mm256_maskz_cvt_roundps_epi64, __m256i, __mmask8, __m128, 8) test_2 (_mm256_maskz_cvt_roundps_epu64, __m256i, __mmask8, __m128, 8) +test_2 (_mm256_maskz_cvt_roundepi64_pd, __m256d, __mmask8, __m256i, 8) +test_2 (_mm256_maskz_cvt_roundepi64_ph, __m128h, __mmask8, __m256i, 8) +test_2 (_mm256_maskz_cvt_roundepi64_ps, __m128, __mmask8, __m256i, 8) +test_2 (_mm256_maskz_cvtt_roundpd_epi32, __m128i, __mmask8, __m256d, 8) +test_2 (_mm256_maskz_cvtt_roundpd_epi64, __m256i, __mmask8, __m256d, 8) +test_2 (_mm256_maskz_cvtt_roundpd_epu32, __m128i, __mmask8, __m256d, 8) +test_2 (_mm256_maskz_cvtt_roundpd_epu64, __m256i, __mmask8, __m256d, 8) test_2x (_mm256_cmp_round_pd_mask, __mmask8, __m256d, __m256d, 1, 8) test_2x (_mm256_cmp_round_ph_mask, __mmask16, __m256h, __m256h, 1, 8) test_2x (_mm256_cmp_round_ps_mask, __mmask8, __m256, __m256, 1, 8) @@ -1098,6 +1112,13 @@ test_3 (_mm256_mask_cvt_roundps_epi32, __m256i, __m256i, __mmask8, __m256, 9) test_3 (_mm256_mask_cvt_roundps_epu32, __m256i, __m256i, __mmask8, __m256, 9) test_3 (_mm256_mask_cvt_roundps_epi64, __m256i, __m256i, __mmask8, __m128, 8) test_3 (_mm256_mask_cvt_roundps_epu64, __m256i, __m256i, __mmask8, __m128, 8) +test_3 (_mm256_mask_cvt_roundepi64_pd, __m256d, __m256d, __mmask8, __m256i, 8) +test_3 (_mm256_mask_cvt_roundepi64_ph, __m128h, __m128h, __mmask8, __m256i, 8) +test_3 (_mm256_mask_cvt_roundepi64_ps, __m128, __m128, __mmask8, __m256i, 8) +test_3 (_mm256_mask_cvtt_roundpd_epi32, __m128i, __m128i, __mmask8, __m256d, 8) +test_3 (_mm256_mask_cvtt_roundpd_epi64, __m256i, __m256i, __mmask8, __m256d, 8) +test_3 (_mm256_mask_cvtt_roundpd_epu32, __m128i, __m128i, __mmask8, __m256d, 8) +test_3 (_mm256_mask_cvtt_roundpd_epu64, __m256i, __m256i, __mmask8, __m256d, 8) test_3x (_mm256_mask_cmp_round_pd_mask, __mmask8, __mmask8, __m256d, __m256d, 1, 8) test_3x (_mm256_mask_cmp_round_ph_mask, __mmask16, __mmask16, __m256h, __m256h, 1, 8) test_3x (_mm256_mask_cmp_round_ps_mask, __mmask8, __mmask8, __m256, __m256, 1, 8) diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc/testsuite/gcc.target/i386/sse-22.c index 593dff8381f..a706f605121 100644 --- a/gcc/testsuite/gcc.target/i386/sse-22.c +++ b/gcc/testsuite/gcc.target/i386/sse-22.c @@ -1085,6 +1085,13 @@ test_1 (_mm256_cvt_roundps_epi32, __m256i, __m256, 9) test_1 (_mm256_cvt_roundps_epu32, __m256i, __m256, 9) test_1 (_mm256_cvt_roundps_epi64, __m256i, __m128, 8) test_1 (_mm256_cvt_roundps_epu64, __m256i, __m128, 8) +test_1 (_mm256_cvt_roundepi64_pd, __m256d, __m256i, 8) +test_1 (_mm256_cvt_roundepi64_ph, __m128h, __m256i, 8) +test_1 (_mm256_cvt_roundepi64_ps, __m128, __m256i, 8) +test_1 (_mm256_cvtt_roundpd_epi32, __m128i, __m256d, 8) +test_1 (_mm256_cvtt_roundpd_epi64, __m256i, __m256d, 8) +test_1 (_mm256_cvtt_roundpd_epu32, __m128i, __m256d, 8) +test_1 (_mm256_cvtt_roundpd_epu64, __m256i, __m256d, 8) test_2 (_mm256_add_round_pd, __m256d, __m256d, __m256d, 9) test_2 (_mm256_add_round_ph, __m256h, __m256h, __m256h, 8) test_2 (_mm256_add_round_ps, __m256, __m256, __m256, 9) @@ -1111,6 +1118,13 @@ test_2 (_mm256_maskz_cvt_roundps_epi32, __m256i, __mmask8, __m256, 9) test_2 (_mm256_maskz_cvt_roundps_epu32, __m256i, __mmask8, __m256, 9) test_2 (_mm256_maskz_cvt_roundps_epi64, __m256i, __mmask8, __m128, 8) test_2 (_mm256_maskz_cvt_roundps_epu64, __m256i, __mmask8, __m128, 8) +test_2 (_mm256_maskz_cvt_roundepi64_pd, __m256d, __mmask8, __m256i, 8) +test_2 (_mm256_maskz_cvt_roundepi64_ph, __m128h, __mmask8, __m256i, 8) +test_2 (_mm256_maskz_cvt_roundepi64_ps, __m128, __mmask8, __m256i, 8) +test_2 (_mm256_maskz_cvtt_roundpd_epi32, __m128i, __mmask8, __m256d, 8) +test_2 (_mm256_maskz_cvtt_roundpd_epi64, __m256i, __mmask8, __m256d, 8) +test_2 (_mm256_maskz_cvtt_roundpd_epu32, __m128i, __mmask8, __m256d, 8) +test_2 (_mm256_maskz_cvtt_roundpd_epu64, __m256i, __mmask8, __m256d, 8) test_2x (_mm256_cmp_round_pd_mask, __mmask8, __m256d, __m256d, 1, 8) test_2x (_mm256_cmp_round_ph_mask, __mmask16, __m256h, __m256h, 1, 8) test_2x (_mm256_cmp_round_ps_mask, __mmask8, __m256, __m256, 1, 8) @@ -1140,6 +1154,13 @@ test_3 (_mm256_mask_cvt_roundps_epi32, __m256i, __m256i, __mmask8, __m256, 9) test_3 (_mm256_mask_cvt_roundps_epu32, __m256i, __m256i, __mmask8, __m256, 9) test_3 (_mm256_mask_cvt_roundps_epi64, __m256i, __m256i, __mmask8, __m128, 8) test_3 (_mm256_mask_cvt_roundps_epu64, __m256i, __m256i, __mmask8, __m128, 8) +test_3 (_mm256_mask_cvt_roundepi64_pd, __m256d, __m256d, __mmask8, __m256i, 8) +test_3 (_mm256_mask_cvt_roundepi64_ph, __m128h, __m128h, __mmask8, __m256i, 8) +test_3 (_mm256_mask_cvt_roundepi64_ps, __m128, __m128, __mmask8, __m256i, 8) +test_3 (_mm256_mask_cvtt_roundpd_epi32, __m128i, __m128i, __mmask8, __m256d, 8) +test_3 (_mm256_mask_cvtt_roundpd_epi64, __m256i, __m256i, __mmask8, __m256d, 8) +test_3 (_mm256_mask_cvtt_roundpd_epu32, __m128i, __m128i, __mmask8, __m256d, 8) +test_3 (_mm256_mask_cvtt_roundpd_epu64, __m256i, __m256i, __mmask8, __m256d, 8) test_3x (_mm256_mask_cmp_round_pd_mask, __mmask8, __mmask8, __m256d, __m256d, 1, 8) test_3x (_mm256_mask_cmp_round_ph_mask, __mmask16, __mmask16, __m256h, __m256h, 1, 8) test_3x (_mm256_mask_cmp_round_ps_mask, __mmask8, __mmask8, __m256, __m256, 1, 8) diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c index d31fec9f2fb..3f7d0acc7c1 100644 --- a/gcc/testsuite/gcc.target/i386/sse-23.c +++ b/gcc/testsuite/gcc.target/i386/sse-23.c @@ -854,6 +854,13 @@ #define __builtin_ia32_cvtps2qq256_mask_round(A, B, C, D) __builtin_ia32_cvtps2qq256_mask_round(A, B, C, 8) #define __builtin_ia32_cvtps2udq256_mask_round(A, B, C, D) __builtin_ia32_cvtps2udq256_mask_round(A, B, C, 8) #define __builtin_ia32_cvtps2uqq256_mask_round(A, B, C, D) __builtin_ia32_cvtps2uqq256_mask_round(A, B, C, 8) +#define __builtin_ia32_cvtqq2pd256_mask_round(A, B, C, D) __builtin_ia32_cvtqq2pd256_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtqq2ph256_mask_round(A, B, C, D) __builtin_ia32_vcvtqq2ph256_mask_round(A, B, C, 8) +#define __builtin_ia32_cvtqq2ps256_mask_round(A, B, C, D) __builtin_ia32_cvtqq2ps256_mask_round(A, B, C, 8) +#define __builtin_ia32_cvttpd2dq256_mask_round(A, B, C, D) __builtin_ia32_cvttpd2dq256_mask_round(A, B, C, 8) +#define __builtin_ia32_cvttpd2qq256_mask_round(A, B, C, D) __builtin_ia32_cvttpd2qq256_mask_round(A, B, C, 8) +#define __builtin_ia32_cvttpd2udq256_mask_round(A, B, C, D) __builtin_ia32_cvttpd2udq256_mask_round(A, B, C, 8) +#define __builtin_ia32_cvttpd2uqq256_mask_round(A, B, C, D) __builtin_ia32_cvttpd2uqq256_mask_round(A, B, C, 8) #pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,sha,xsavec,xsaves,clflushopt,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,vpclmulqdq,pconfig,wbnoinvd,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2-512")

[07/22] AVX10.2 ymm rounding: Support vcvtqq2p{s, d, h} and vcvttpd2{, u}{dq, qq} intrins

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Patch