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X-CSE-ConnectionGUID: Um5fhdvpRyeoOpXz/hZ+pQ== X-CSE-MsgGUID: vNbu+itLT9qUSn7khaEp8Q== X-IronPort-AV: E=McAfee;i="6700,10204,11163"; a="13003745" X-IronPort-AV: E=Sophos;i="6.09,288,1716274800"; d="scan'208";a="13003745" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2024 02:04:05 -0700 X-CSE-ConnectionGUID: U5/pKKBXTpa+1OqospcfXg== X-CSE-MsgGUID: nNd1yA6TRDuo3lTBwO95Sw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,288,1716274800"; d="scan'208";a="58649833" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmviesa007.fm.intel.com with ESMTP; 14 Aug 2024 02:04:02 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 354DC1007014; Wed, 14 Aug 2024 17:04:01 +0800 (CST) From: Haochen Jiang To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com, ubizjak@gmail.com, "Hu, Lin1" Subject: [PATCH 02/22] AVX10.2 ymm rounding: Support vcvtdq2p{s, h} and vcvtpd2p{s, h} intrins Date: Wed, 14 Aug 2024 17:01:39 +0800 Message-Id: <20240814090159.422097-3-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20240814090159.422097-1-haochen.jiang@intel.com> References: <20240814090159.422097-1-haochen.jiang@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: "Hu, Lin1" gcc/ChangeLog: * config/i386/avx10_2roundingintrin.h: Add new intrins. * config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle V8SF_FTYPE_V8SI_V8SF_UQI_INT, V4SF_FTYPE_V4DF_V4SF_UQI_INT, V8HF_FTYPE_V8SI_V8HF_UQI_INT, V8HF_FTYPE_V4DF_V8HF_UQI_INT. * config/i386/sse.md: (avx512fp16_vcvt2ph_): Add condition check. (avx512fp16_vcvtpd2ph_v4df_mask_round): New expand. (*avx512fp16_vcvt2ph__mask): Change name to avx512fp16_vcvt2ph__mask_1 and extend pattern to generate 256bit insns. (avx_cvtpd2ps256): Change name to avx_cvtpd2ps256 and extend pattern to generate 256bit insns. * config/i386/subst.md (round_applied): New condition. (round_suff): New iterator. (round_mode_condition): Add V32HI check for 512bit. (round_saeonly_mode_condition): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/avx-1.c: Add new builtin test. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/sse-14.c: Add new macro test. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/avx10_2-rounding-1.c: Add test. --- gcc/config/i386/avx10_2roundingintrin.h | 210 ++++++++++++++++++ gcc/config/i386/i386-builtin-types.def | 4 + gcc/config/i386/i386-builtin.def | 4 + gcc/config/i386/i386-expand.cc | 4 + gcc/config/i386/sse.md | 32 ++- gcc/config/i386/subst.md | 4 + gcc/testsuite/gcc.target/i386/avx-1.c | 4 + .../gcc.target/i386/avx10_2-rounding-1.c | 44 +++- gcc/testsuite/gcc.target/i386/sse-13.c | 4 + gcc/testsuite/gcc.target/i386/sse-14.c | 12 + gcc/testsuite/gcc.target/i386/sse-22.c | 12 + gcc/testsuite/gcc.target/i386/sse-23.c | 4 + 12 files changed, 322 insertions(+), 16 deletions(-) diff --git a/gcc/config/i386/avx10_2roundingintrin.h b/gcc/config/i386/avx10_2roundingintrin.h index 5698ed05c1d..09285c1ffcd 100644 --- a/gcc/config/i386/avx10_2roundingintrin.h +++ b/gcc/config/i386/avx10_2roundingintrin.h @@ -216,6 +216,138 @@ _mm256_mask_cmp_round_ps_mask (__mmask8 __U, __m256 __A, __m256 __B, (__mmask8) __U, __R); } + +extern __inline __m128h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_cvt_roundepi32_ph (__m256i __A, const int __R) +{ + return (__m128h) __builtin_ia32_vcvtdq2ph256_mask_round ((__v8si) __A, + (__v8hf) + _mm_setzero_ph (), + (__mmask8) -1, + __R); +} + +extern __inline __m128h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_cvt_roundepi32_ph (__m128h __W, __mmask8 __U, __m256i __A, + const int __R) +{ + return (__m128h) __builtin_ia32_vcvtdq2ph256_mask_round ((__v8si) __A, + (__v8hf) __W, + (__mmask8) __U, + __R); +} + +extern __inline __m128h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_cvt_roundepi32_ph (__mmask8 __U, __m256i __A, const int __R) +{ + return (__m128h) __builtin_ia32_vcvtdq2ph256_mask_round ((__v8si) __A, + (__v8hf) + _mm_setzero_ph (), + (__mmask8) __U, + __R); +} + +extern __inline __m256 +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_cvt_roundepi32_ps (__m256i __A, const int __R) +{ + return (__m256) __builtin_ia32_cvtdq2ps256_mask_round ((__v8si) __A, + (__v8sf) + _mm256_undefined_ps (), + (__mmask8) -1, + __R); +} + +extern __inline __m256 +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_cvt_roundepi32_ps (__m256 __W, __mmask8 __U, __m256i __A, + const int __R) +{ + return (__m256) __builtin_ia32_cvtdq2ps256_mask_round ((__v8si) __A, + (__v8sf) __W, + (__mmask8) __U, + __R); +} + +extern __inline __m256 +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_cvt_roundepi32_ps (__mmask8 __U, __m256i __A, const int __R) +{ + return (__m256) __builtin_ia32_cvtdq2ps256_mask_round ((__v8si) __A, + (__v8sf) + _mm256_setzero_ps (), + (__mmask8) __U, + __R); +} + +extern __inline __m128h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_cvt_roundpd_ph (__m256d __A, const int __R) +{ + return (__m128h) __builtin_ia32_vcvtpd2ph256_mask_round ((__v4df) __A, + (__v8hf) + _mm_setzero_ph (), + (__mmask8) -1, + __R); +} + +extern __inline __m128h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_cvt_roundpd_ph (__m128h __W, __mmask8 __U, __m256d __A, + const int __R) +{ + return (__m128h) __builtin_ia32_vcvtpd2ph256_mask_round ((__v4df) __A, + (__v8hf) __W, + (__mmask8) __U, + __R); +} + +extern __inline __m128h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_cvt_roundpd_ph (__mmask8 __U, __m256d __A, const int __R) +{ + return (__m128h) __builtin_ia32_vcvtpd2ph256_mask_round ((__v4df) __A, + (__v8hf) + _mm_setzero_ph (), + (__mmask8) __U, + __R); +} + +extern __inline __m128 +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_cvt_roundpd_ps (__m256d __A, const int __R) +{ + return (__m128) __builtin_ia32_cvtpd2ps256_mask_round ((__v4df) __A, + (__v4sf) + _mm_undefined_ps (), + (__mmask8) -1, + __R); +} + +extern __inline __m128 +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_cvt_roundpd_ps (__m128 __W, __mmask8 __U, __m256d __A, + const int __R) +{ + return (__m128) __builtin_ia32_cvtpd2ps256_mask_round ((__v4df) __A, + (__v4sf) __W, + (__mmask8) __U, + __R); +} + +extern __inline __m128 +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_cvt_roundpd_ps (__mmask8 __U, __m256d __A, const int __R) +{ + return (__m128) __builtin_ia32_cvtpd2ps256_mask_round ((__v4df) __A, + (__v4sf) + _mm_setzero_ps (), + (__mmask8) __U, + __R); +} #else #define _mm256_add_round_pd(A, B, R) \ ((__m256d) __builtin_ia32_addpd256_mask_round ((__v4df) (A), \ @@ -327,6 +459,84 @@ _mm256_mask_cmp_round_ps_mask (__mmask8 __U, __m256 __A, __m256 __B, (C), \ (__mmask8) (U), \ (R))) + +#define _mm256_cvt_roundepi32_ph(A, R) \ + ((__m128h) __builtin_ia32_vcvtdq2ph256_mask_round ((__v8si) (A), \ + (__v8hf) \ + (_mm_setzero_ph ()), \ + (__mmask8) (-1), \ + (R))) + +#define _mm256_mask_cvt_roundepi32_ph(W, U, A, R) \ + ((__m128h) __builtin_ia32_vcvtdq2ph256_mask_round ((__v8si) (A), \ + (__v8hf) (W), \ + (__mmask8) (U), \ + (R))) + +#define _mm256_maskz_cvt_roundepi32_ph(U, A, R) \ + ((__m128h) __builtin_ia32_vcvtdq2ph256_mask_round ((__v8si) (A), \ + (__v8hf) \ + (_mm_setzero_ph ()), \ + (__mmask8) (U), \ + (R))) + +#define _mm256_cvt_roundepi32_ps(A, R) \ + ((__m256) __builtin_ia32_cvtdq2ps256_mask_round ((__v8si) (A), \ + (__v8sf) \ + (_mm256_undefined_ps ()), \ + (__mmask8) (-1), \ + (R))) + +#define _mm256_mask_cvt_roundepi32_ps(W, U, A, R) \ + ((__m256) __builtin_ia32_cvtdq2ps256_mask_round ((__v8si) (A), \ + (__v8sf) (W), \ + (__mmask8) (U), \ + (R))) + +#define _mm256_maskz_cvt_roundepi32_ps(U, A, R) \ + ((__m256) __builtin_ia32_cvtdq2ps256_mask_round ((__v8si) (A), \ + (__v8sf) \ + (_mm256_setzero_ps ()), \ + (__mmask8) (U), \ + (R))) + +#define _mm256_cvt_roundpd_ph(A, R) \ + ((__m128h) __builtin_ia32_vcvtpd2ph256_mask_round ((__v4df) (A), \ + (_mm_setzero_ph ()), \ + (__mmask8) (-1), \ + (R))) + +#define _mm256_mask_cvt_roundpd_ph(W, U, A, R) \ + ((__m128h) __builtin_ia32_vcvtpd2ph256_mask_round ((__v4df) (A), \ + (__v8hf) (W), \ + (__mmask8) (U), \ + (R))) + +#define _mm256_maskz_cvt_roundpd_ph(U, A, R) \ + ((__m128h) __builtin_ia32_vcvtpd2ph256_mask_round ((__v4df) (A), \ + (_mm_setzero_ph ()), \ + (__mmask8) (U), \ + (R))) + +#define _mm256_cvt_roundpd_ps(A, R) \ + ((__m128) __builtin_ia32_cvtpd2ps256_mask_round ((__v4df) (A), \ + (__v4sf) \ + (_mm_undefined_ps ()), \ + (__mmask8) (-1), \ + (R))) + +#define _mm256_mask_cvt_roundpd_ps(W, U, A, R) \ + ((__m128) __builtin_ia32_cvtpd2ps256_mask_round ((__v4df) (A), \ + (__v4sf) (W), \ + (__mmask8) (U), \ + (R))) + +#define _mm256_maskz_cvt_roundpd_ps(U, A, R) \ + ((__m128) __builtin_ia32_cvtpd2ps256_mask_round ((__v4df) (A), \ + (__v4sf) \ + (_mm_setzero_ps ()), \ + (__mmask8) (U), \ + (R))) #endif #ifdef __DISABLE_AVX10_2_256__ diff --git a/gcc/config/i386/i386-builtin-types.def b/gcc/config/i386/i386-builtin-types.def index f32abfd9d70..ec788841f8d 100644 --- a/gcc/config/i386/i386-builtin-types.def +++ b/gcc/config/i386/i386-builtin-types.def @@ -1421,3 +1421,7 @@ DEF_FUNCTION_TYPE (V8SF, V8SF, V8SF, V8SF, UQI, INT) DEF_FUNCTION_TYPE (UQI, V4DF, V4DF, INT, UQI, INT) DEF_FUNCTION_TYPE (UHI, V16HF, V16HF, INT, UHI, INT) DEF_FUNCTION_TYPE (UQI, V8SF, V8SF, INT, UQI, INT) +DEF_FUNCTION_TYPE (V8HF, V8SI, V8HF, UQI, INT) +DEF_FUNCTION_TYPE (V8SF, V8SI, V8SF, UQI, INT) +DEF_FUNCTION_TYPE (V8HF, V4DF, V8HF, UQI, INT) +DEF_FUNCTION_TYPE (V4SF, V4DF, V4SF, UQI, INT) diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index a7c0884e2ab..38920bb2e26 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -3325,6 +3325,10 @@ BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_addv8sf3_mask_round, "__builtin BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_cmpv4df3_mask_round, "__builtin_ia32_cmppd256_mask_round", IX86_BUILTIN_CMPPD256_MASK_ROUND, UNKNOWN, (int) UQI_FTYPE_V4DF_V4DF_INT_UQI_INT) BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_cmpv16hf3_mask_round, "__builtin_ia32_cmpph256_mask_round", IX86_BUILTIN_CMPPH256_MASK_ROUND, UNKNOWN, (int) UHI_FTYPE_V16HF_V16HF_INT_UHI_INT) BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_cmpv8sf3_mask_round, "__builtin_ia32_cmpps256_mask_round", IX86_BUILTIN_CMPPS256_MASK_ROUND, UNKNOWN, (int) UQI_FTYPE_V8SF_V8SF_INT_UQI_INT) +BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512fp16_vcvtdq2ph_v8si_mask_round, "__builtin_ia32_vcvtdq2ph256_mask_round", IX86_BUILTIN_VCVTDQ2PH256_MASK_ROUND, UNKNOWN, (int) V8HF_FTYPE_V8SI_V8HF_UQI_INT) +BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_floatv8siv8sf2_mask_round, "__builtin_ia32_cvtdq2ps256_mask_round", IX86_BUILTIN_VCVTDQ2PS256_MASK_ROUND, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_UQI_INT) +BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512fp16_vcvtpd2ph_v4df_mask_round, "__builtin_ia32_vcvtpd2ph256_mask_round", IX86_BUILTIN_VCVTPD2PH256_MASK_ROUND, UNKNOWN, (int) V8HF_FTYPE_V4DF_V8HF_UQI_INT) +BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx_cvtpd2ps256_mask_round, "__builtin_ia32_cvtpd2ps256_mask_round", IX86_BUILTIN_CVTPD2PS256_MASK_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4DF_V4SF_UQI_INT) BDESC_END (ROUND_ARGS, MULTI_ARG) diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index af94087c6d5..b6fc873a0b7 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -12464,10 +12464,14 @@ ix86_expand_round_builtin (const struct builtin_description *d, case V16HF_FTYPE_V16SI_V16HF_UHI_INT: case V8DF_FTYPE_V8SF_V8DF_QI_INT: case V16SF_FTYPE_V16HI_V16SF_HI_INT: + case V8SF_FTYPE_V8SI_V8SF_UQI_INT: case V2DF_FTYPE_V2DF_V2DF_V2DF_INT: + case V4SF_FTYPE_V4DF_V4SF_UQI_INT: case V4SF_FTYPE_V4SF_V4SF_V4SF_INT: case V8HF_FTYPE_V8DI_V8HF_UQI_INT: case V8HF_FTYPE_V8DF_V8HF_UQI_INT: + case V8HF_FTYPE_V8SI_V8HF_UQI_INT: + case V8HF_FTYPE_V4DF_V8HF_UQI_INT: case V16HF_FTYPE_V16SF_V16HF_UHI_INT: case V8HF_FTYPE_V8HF_V8HF_V8HF_INT: nargs = 4; diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index acc1dc66491..210f6988aaf 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -7384,7 +7384,7 @@ [(set (match_operand: 0 "register_operand" "=v") (any_float: (match_operand:VI2H_AVX512VL 1 "" "")))] - "TARGET_AVX512FP16" + "TARGET_AVX512FP16 && " "vcvt2ph\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "evex") @@ -7889,6 +7889,19 @@ (set_attr "prefix" "evex") (set_attr "mode" "")]) +(define_expand "avx512fp16_vcvtpd2ph_v4df_mask_round" + [(match_operand:V8HF 0 "register_operand") + (match_operand:V4DF 1 "register_operand") + (match_operand:V8HF 2 "nonimm_or_0_operand") + (match_operand:QI 3 "register_operand") + (unspec [(match_operand:SI 4 "const_4_or_8_to_11_operand")] UNSPEC_EMBEDDED_ROUNDING)] + "TARGET_AVX10_2_256" +{ + emit_insn (gen_avx512fp16_vcvtpd2ph_v4df_mask_round_1 ( + operands[0], operands[1], operands[2], operands[3], CONST0_RTX (V4HFmode), operands[4])); + DONE; +}) + (define_expand "avx512fp16_vcvt2ph__mask" [(set (match_operand:V8HF 0 "register_operand" "=v") (vec_concat:V8HF @@ -7904,20 +7917,20 @@ "TARGET_AVX512FP16 && TARGET_AVX512VL" "operands[4] = CONST0_RTX (V4HFmode);") -(define_insn "*avx512fp16_vcvt2ph__mask" +(define_insn "avx512fp16_vcvt2ph__mask_1" [(set (match_operand:V8HF 0 "register_operand" "=v") (vec_concat:V8HF (vec_merge:V4HF (float_truncate:V4HF - (match_operand:VF4_128_8_256 1 "vector_operand" "vm")) + (match_operand:VF4_128_8_256 1 "" "")) (vec_select:V4HF (match_operand:V8HF 2 "nonimm_or_0_operand" "0C") (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)])) (match_operand:QI 3 "register_operand" "Yk")) (match_operand:V4HF 4 "const0_operand")))] - "TARGET_AVX512FP16 && TARGET_AVX512VL" - "vcvt2ph\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" + "TARGET_AVX512FP16 && TARGET_AVX512VL && " + "vcvt2ph\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "evex") (set_attr "mode" "")]) @@ -9813,12 +9826,13 @@ (set_attr "prefix" "evex") (set_attr "mode" "V8SF")]) -(define_insn "avx_cvtpd2ps256" +(define_insn "avx_cvtpd2ps256" [(set (match_operand:V4SF 0 "register_operand" "=v") (float_truncate:V4SF - (match_operand:V4DF 1 "nonimmediate_operand" "vm")))] - "TARGET_AVX && " - "vcvtpd2ps{y}\t{%1, %0|%0, %1}" + (match_operand:V4DF 1 "" "")))] + "TARGET_AVX && + && (! || TARGET_AVX10_2_256)" + "vcvtpd2ps\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "maybe_evex") (set_attr "btver2_decode" "vector") diff --git a/gcc/config/i386/subst.md b/gcc/config/i386/subst.md index ba180301b90..ea3ad9a206a 100644 --- a/gcc/config/i386/subst.md +++ b/gcc/config/i386/subst.md @@ -197,6 +197,7 @@ (define_subst_attr "round_sd_mask_op4" "round" "" "") (define_subst_attr "round_sdc_mask_op4" "round" "" "") (define_subst_attr "round_constraint" "round" "vm" "v") +(define_subst_attr "round_suff" "round" "{y}" "") (define_subst_attr "round_qq2phsuff" "round" "" "") (define_subst_attr "bcst_round_constraint" "round" "vmBr" "v") (define_subst_attr "round_constraint2" "round" "m" "v") @@ -209,6 +210,7 @@ || mode == V8DFmode || mode == V8DImode || mode == V16SImode + || mode == V32HImode || mode == V32HFmode) || (TARGET_AVX10_2_256 && (mode == V8SFmode @@ -216,6 +218,7 @@ || mode == V4DImode || mode == V8SImode || mode == V16HFmode)))") +(define_subst_attr "round_applied" "round" "false" "true") (define_subst_attr "round_modev4sf_condition" "round" "1" "(mode == V4SFmode)") (define_subst_attr "round_codefor" "round" "*" "") @@ -260,6 +263,7 @@ || mode == V8DFmode || mode == V8DImode || mode == V16SImode + || mode == V32HImode || mode == V32HFmode) || (TARGET_AVX10_2_256 && (mode == V8SFmode diff --git a/gcc/testsuite/gcc.target/i386/avx-1.c b/gcc/testsuite/gcc.target/i386/avx-1.c index 8b852c670cd..3d7d4231124 100644 --- a/gcc/testsuite/gcc.target/i386/avx-1.c +++ b/gcc/testsuite/gcc.target/i386/avx-1.c @@ -849,6 +849,10 @@ #define __builtin_ia32_cmppd256_mask_round(A, B, C, D, E) __builtin_ia32_cmppd256_mask_round(A, B, 1, D, 8) #define __builtin_ia32_cmpph256_mask_round(A, B, C, D, E) __builtin_ia32_cmpph256_mask_round(A, B, 1, D, 8) #define __builtin_ia32_cmpps256_mask_round(A, B, C, D, E) __builtin_ia32_cmpps256_mask_round(A, B, 1, D, 8) +#define __builtin_ia32_vcvtdq2ph256_mask_round(A, B, C, D) __builtin_ia32_vcvtdq2ph256_mask_round(A, B, C, 8) +#define __builtin_ia32_cvtdq2ps256_mask_round(A, B, C, D) __builtin_ia32_cvtdq2ps256_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtpd2ph256_mask_round(A, B, C, D) __builtin_ia32_vcvtpd2ph256_mask_round(A, B, C, 8) +#define __builtin_ia32_cvtpd2ps256_mask_round(A, B, C, D) __builtin_ia32_cvtpd2ps256_mask_round(A, B, C, 8) #include #include diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-rounding-1.c b/gcc/testsuite/gcc.target/i386/avx10_2-rounding-1.c index 0fd37bc8c3c..bf77164729d 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-rounding-1.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-rounding-1.c @@ -15,12 +15,27 @@ /* { dg-final { scan-assembler-times "vcmpph\[ \\t\]+\[^\{\n\]*\\\$4\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%k\[0-9\]\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcmpps\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%ymm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vcmpps\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%ymm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtdq2phy\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtdq2ph\[ \\t\]+\{rn-sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtdq2ph\[ \\t\]+\{rz-sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtdq2ps\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtdq2ps\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtdq2ps\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtpd2phy\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtpd2ph\[ \\t\]+\{rn-sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtpd2ph\[ \\t\]+\{rz-sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtpd2ps\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtpd2ps\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtpd2ps\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ #include +volatile __m128 hx; +volatile __m128h hxh; volatile __m256 x; volatile __m256d xd; volatile __m256h xh; +volatile __m256i xi; volatile __mmask8 m8; volatile __mmask16 m16; volatile __mmask32 m32; @@ -39,7 +54,11 @@ avx10_2_test_1 (void) x = _mm256_add_round_ps (x, x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC); x = _mm256_mask_add_round_ps (x, m16, x, x, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC); x = _mm256_maskz_add_round_ps (m16, x, x, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC); +} +void extern +avx10_2_test_2 (void) +{ m8 = _mm256_cmp_round_pd_mask (xd, xd, _CMP_FALSE_OQ, _MM_FROUND_NO_EXC); m8 = _mm256_mask_cmp_round_pd_mask (m8, xd, xd, _CMP_FALSE_OQ, _MM_FROUND_NO_EXC); @@ -51,14 +70,25 @@ avx10_2_test_1 (void) } void extern -avx10_2_test_2 (void) +avx10_2_test_3 (void) { - m8 = _mm256_cmp_round_pd_mask (xd, xd, _CMP_FALSE_OQ, _MM_FROUND_NO_EXC); - m8 = _mm256_mask_cmp_round_pd_mask (m8, xd, xd, _CMP_FALSE_OQ, _MM_FROUND_NO_EXC); + hxh = _mm256_cvt_roundepi32_ph (xi, 4); + hxh = _mm256_mask_cvt_roundepi32_ph (hxh, m8, xi, 8); + hxh = _mm256_maskz_cvt_roundepi32_ph (m8, xi, 11); - m16 = _mm256_cmp_round_ph_mask (xh, xh, 3, 8); - m16 = _mm256_mask_cmp_round_ph_mask (m16, xh, xh, 4, 4); + x = _mm256_cvt_roundepi32_ps (xi, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC); + x = _mm256_mask_cvt_roundepi32_ps (x, m8, xi, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC); + x = _mm256_maskz_cvt_roundepi32_ps (m8, xi, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC); +} - m8 = _mm256_cmp_round_ps_mask (x, x, _CMP_FALSE_OQ, _MM_FROUND_NO_EXC); - m8 = _mm256_mask_cmp_round_ps_mask (m8, x, x, _CMP_FALSE_OQ, _MM_FROUND_NO_EXC); +void extern +avx10_2_test_4 (void) +{ + hxh = _mm256_cvt_roundpd_ph (xd, 4); + hxh = _mm256_mask_cvt_roundpd_ph (hxh, m8, xd, 8); + hxh = _mm256_maskz_cvt_roundpd_ph (m8, xd, 11); + + hx = _mm256_cvt_roundpd_ps (xd, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC); + hx = _mm256_mask_cvt_roundpd_ps (hx, 4, xd, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC); + hx = _mm256_maskz_cvt_roundpd_ps (6, xd, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC); } diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c index 3b0f96ac8d9..c1d6486f560 100644 --- a/gcc/testsuite/gcc.target/i386/sse-13.c +++ b/gcc/testsuite/gcc.target/i386/sse-13.c @@ -856,5 +856,9 @@ #define __builtin_ia32_cmppd256_mask_round(A, B, C, D, E) __builtin_ia32_cmppd256_mask_round(A, B, 1, D, 8) #define __builtin_ia32_cmpph256_mask_round(A, B, C, D, E) __builtin_ia32_cmpph256_mask_round(A, B, 1, D, 8) #define __builtin_ia32_cmpps256_mask_round(A, B, C, D, E) __builtin_ia32_cmpps256_mask_round(A, B, 1, D, 8) +#define __builtin_ia32_vcvtdq2ph256_mask_round(A, B, C, D) __builtin_ia32_vcvtdq2ph256_mask_round(A, B, C, 8) +#define __builtin_ia32_cvtdq2ps256_mask_round(A, B, C, D) __builtin_ia32_cvtdq2ps256_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtpd2ph256_mask_round(A, B, C, D) __builtin_ia32_vcvtpd2ph256_mask_round(A, B, C, 8) +#define __builtin_ia32_cvtpd2ps256_mask_round(A, B, C, D) __builtin_ia32_cvtpd2ps256_mask_round(A, B, C, 8) #include diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc/testsuite/gcc.target/i386/sse-14.c index 9f0a4c19418..2a5ab69135b 100644 --- a/gcc/testsuite/gcc.target/i386/sse-14.c +++ b/gcc/testsuite/gcc.target/i386/sse-14.c @@ -1021,15 +1021,27 @@ test_2 (_mm512_gf2p8affine_epi64_epi8, __m512i, __m512i, __m512i, 1) test_3 (_mm_sm3rnds2_epi32, __m128i, __m128i, __m128i, __m128i, 1) /* avx10_2roundingintrin.h */ +test_1 (_mm256_cvt_roundepi32_ph, __m128h, __m256i, 8) +test_1 (_mm256_cvt_roundepi32_ps, __m256, __m256i, 9) +test_1 (_mm256_cvt_roundpd_ph, __m128h, __m256d, 8) +test_1 (_mm256_cvt_roundpd_ps, __m128, __m256d, 9) test_2 (_mm256_add_round_pd, __m256d, __m256d, __m256d, 9) test_2 (_mm256_add_round_ph, __m256h, __m256h, __m256h, 8) test_2 (_mm256_add_round_ps, __m256, __m256, __m256, 9) +test_2 (_mm256_maskz_cvt_roundepi32_ph, __m128h, __mmask8, __m256i, 8) +test_2 (_mm256_maskz_cvt_roundepi32_ps, __m256, __mmask8, __m256i, 9) +test_2 (_mm256_maskz_cvt_roundpd_ph, __m128h, __mmask8, __m256d, 8) +test_2 (_mm256_maskz_cvt_roundpd_ps, __m128, __mmask8, __m256d, 9) test_2x (_mm256_cmp_round_pd_mask, __mmask8, __m256d, __m256d, 1, 8) test_2x (_mm256_cmp_round_ph_mask, __mmask16, __m256h, __m256h, 1, 8) test_2x (_mm256_cmp_round_ps_mask, __mmask8, __m256, __m256, 1, 8) test_3 (_mm256_maskz_add_round_pd, __m256d, __mmask8, __m256d, __m256d, 9) test_3 (_mm256_maskz_add_round_ph, __m256h, __mmask16, __m256h, __m256h, 8) test_3 (_mm256_maskz_add_round_ps, __m256, __mmask8, __m256, __m256, 9) +test_3 (_mm256_mask_cvt_roundepi32_ph, __m128h, __m128h, __mmask8, __m256i, 8) +test_3 (_mm256_mask_cvt_roundepi32_ps, __m256, __m256, __mmask8, __m256i, 9) +test_3 (_mm256_mask_cvt_roundpd_ph, __m128h, __m128h, __mmask8, __m256d, 8) +test_3 (_mm256_mask_cvt_roundpd_ps, __m128, __m128, __mmask8, __m256d, 9) test_3x (_mm256_mask_cmp_round_pd_mask, __mmask8, __mmask8, __m256d, __m256d, 1, 8) test_3x (_mm256_mask_cmp_round_ph_mask, __mmask16, __mmask16, __m256h, __m256h, 1, 8) test_3x (_mm256_mask_cmp_round_ps_mask, __mmask8, __mmask8, __m256, __m256, 1, 8) diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc/testsuite/gcc.target/i386/sse-22.c index 959cec5d23b..32be2373a8b 100644 --- a/gcc/testsuite/gcc.target/i386/sse-22.c +++ b/gcc/testsuite/gcc.target/i386/sse-22.c @@ -1062,15 +1062,27 @@ test_1 ( __bextri_u64, unsigned long long, unsigned long long, 1) test_3 (_mm_sm3rnds2_epi32, __m128i, __m128i, __m128i, __m128i, 1) /* avx10_2roundingintrin.h */ +test_1 (_mm256_cvt_roundepi32_ph, __m128h, __m256i, 8) +test_1 (_mm256_cvt_roundepi32_ps, __m256, __m256i, 9) +test_1 (_mm256_cvt_roundpd_ph, __m128h, __m256d, 8) +test_1 (_mm256_cvt_roundpd_ps, __m128, __m256d, 9) test_2 (_mm256_add_round_pd, __m256d, __m256d, __m256d, 9) test_2 (_mm256_add_round_ph, __m256h, __m256h, __m256h, 8) test_2 (_mm256_add_round_ps, __m256, __m256, __m256, 9) +test_2 (_mm256_maskz_cvt_roundepi32_ph, __m128h, __mmask8, __m256i, 8) +test_2 (_mm256_maskz_cvt_roundepi32_ps, __m256, __mmask8, __m256i, 9) +test_2 (_mm256_maskz_cvt_roundpd_ph, __m128h, __mmask8, __m256d, 8) +test_2 (_mm256_maskz_cvt_roundpd_ps, __m128, __mmask8, __m256d, 9) test_2x (_mm256_cmp_round_pd_mask, __mmask8, __m256d, __m256d, 1, 8) test_2x (_mm256_cmp_round_ph_mask, __mmask16, __m256h, __m256h, 1, 8) test_2x (_mm256_cmp_round_ps_mask, __mmask8, __m256, __m256, 1, 8) test_3 (_mm256_maskz_add_round_pd, __m256d, __mmask8, __m256d, __m256d, 9) test_3 (_mm256_maskz_add_round_ph, __m256h, __mmask16, __m256h, __m256h, 8) test_3 (_mm256_maskz_add_round_ps, __m256, __mmask8, __m256, __m256, 9) +test_3 (_mm256_mask_cvt_roundepi32_ph, __m128h, __m128h, __mmask8, __m256i, 8) +test_3 (_mm256_mask_cvt_roundepi32_ps, __m256, __m256, __mmask8, __m256i, 9) +test_3 (_mm256_mask_cvt_roundpd_ph, __m128h, __m128h, __mmask8, __m256d, 8) +test_3 (_mm256_mask_cvt_roundpd_ps, __m128, __m128, __mmask8, __m256d, 9) test_3x (_mm256_mask_cmp_round_pd_mask, __mmask8, __mmask8, __m256d, __m256d, 1, 8) test_3x (_mm256_mask_cmp_round_ph_mask, __mmask16, __mmask16, __m256h, __m256h, 1, 8) test_3x (_mm256_mask_cmp_round_ps_mask, __mmask8, __mmask8, __m256, __m256, 1, 8) diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c index 0bc7fa00e61..0a3d61fbdd7 100644 --- a/gcc/testsuite/gcc.target/i386/sse-23.c +++ b/gcc/testsuite/gcc.target/i386/sse-23.c @@ -831,6 +831,10 @@ #define __builtin_ia32_cmppd256_mask_round(A, B, C, D, E) __builtin_ia32_cmppd256_mask_round(A, B, 1, D, 8) #define __builtin_ia32_cmpph256_mask_round(A, B, C, D, E) __builtin_ia32_cmpph256_mask_round(A, B, 1, D, 8) #define __builtin_ia32_cmpps256_mask_round(A, B, C, D, E) __builtin_ia32_cmpps256_mask_round(A, B, 1, D, 8) +#define __builtin_ia32_vcvtdq2ph256_mask_round(A, B, C, D) __builtin_ia32_vcvtdq2ph256_mask_round(A, B, C, 8) +#define __builtin_ia32_cvtdq2ps256_mask_round(A, B, C, D) __builtin_ia32_cvtdq2ps256_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtpd2ph256_mask_round(A, B, C, D) __builtin_ia32_vcvtpd2ph256_mask_round(A, B, C, 8) +#define __builtin_ia32_cvtpd2ps256_mask_round(A, B, C, D) __builtin_ia32_cvtpd2ps256_mask_round(A, B, C, 8) #pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,sha,xsavec,xsaves,clflushopt,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,vpclmulqdq,pconfig,wbnoinvd,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2-512")