[20/22] AVX10.2 ymm rounding: Support vreducep{s, d, h} and vrndscalep{s, d, h} intrins

Message ID	20240814090159.422097-21-haochen.jiang@intel.com
State	New
Headers	show Return-Path: <gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org> DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 838F3385DDD9 From: Haochen Jiang <haochen.jiang@intel.com> To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com, ubizjak@gmail.com, "Hu, Lin1" <lin1.hu@intel.com> Subject: [PATCH 20/22] AVX10.2 ymm rounding: Support vreducep{s, d, h} and vrndscalep{s, d, h} intrins Date: Wed, 14 Aug 2024 17:01:57 +0800 Message-Id: <20240814090159.422097-21-haochen.jiang@intel.com> In-Reply-To: <20240814090159.422097-1-haochen.jiang@intel.com> References: <20240814090159.422097-1-haochen.jiang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: list Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org
Series	Support AVX10.2 ymm rounding \| expand [00/22] Support AVX10.2 ymm rounding [01/22] AVX10.2 ymm rounding: Support vadd{s, d, h} and vcmp{s, d, h} intrins [02/22] AVX10.2 ymm rounding: Support vcvtdq2p{s, h} and vcvtpd2p{s, h} intrins [03/22] AVX10.2 ymm rounding: Support vcvtpd2{, u}{dq, qq} intrins [04/22] AVX10.2 ymm rounding: Support vcvtph2p{s, d, sx} and vcvtph2{, u}{dq, qq} intrins [05/22] AVX10.2 ymm rounding: Support vcvtph2{, u}w and vcvtps2p{d, hx} intrins [06/22] AVX10.2 ymm rounding: Support vcvtps2{, u}{dq, qq} intrins [07/22] AVX10.2 ymm rounding: Support vcvtqq2p{s, d, h} and vcvttpd2{, u}{dq, qq} intrins [08/22] AVX10.2 ymm rounding: Support vcvttph2{, u}{dq, qq, w} intrins [09/22] AVX10.2 ymm rounding: Support vcvttps2{, u}{dq, qq} and vcvtu{dq, qq}2p{s, d, h} intrins [10/22] AVX10.2 ymm rounding: Support vcvt{, u}w2ph and vdivp{s, d, h} intrins [11/22] AVX10.2 ymm rounding: Support vfc{madd, mul}cph, vfixupimmp{s, d} intrins [12/22] AVX10.2 ymm rounding: Support vfmadd{132, 231, 213}p{s, d, h} intrins [13/22] AVX10.2 ymm rounding: Support vfmaddcph and vfmaddsub{132, 231, 213}p{s, d, h} intrins [14/22] AVX10.2 ymm rounding: Support vfm{sub, subadd}{132, 231, 213}p{s, d, h} intrins [15/22] AVX10.2 ymm rounding: Support vfmulcph and vfnmadd{132, 231, 213}p{s, d, h} intrins [16/22] AVX10.2 ymm rounding: Support vfnmsub{132, 231, 213}p{s, d, h} intrins [17/22] AVX10.2 ymm rounding: Support vgetexpp{s, d, h} and vgetmantp{s, d, h} intrins [18/22] AVX10.2 ymm rounding: Support v{max, min}p{s, d, h} intrins [19/22] AVX10.2 ymm rounding: Support vmulp{s, d, h} and vrangep{s, d} intrins [20/22] AVX10.2 ymm rounding: Support vreducep{s, d, h} and vrndscalep{s, d, h} intrins [21/22] AVX10.2 ymm rounding: Support vscalefp{s,d,h} intrins [22/22] AVX10.2 ymm rounding: Support vsqrtp{s, d, h} and vsubp{s, d, h} intrins

diff --git a/gcc/config/i386/avx10_2roundingintrin.h b/gcc/config/i386/avx10_2roundingintrin.h index ac0914415c9..d6b8e2695de 100644 --- a/gcc/config/i386/avx10_2roundingintrin.h +++ b/gcc/config/i386/avx10_2roundingintrin.h @@ -3646,6 +3646,233 @@ _mm256_maskz_range_round_ps (__mmask8 __U, __m256 __A, __m256 __B, (__mmask8) __U, __R); } + +extern __inline __m256d +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_reduce_round_pd (__m256d __A, const int __C, const int __R) +{ + return (__m256d) __builtin_ia32_reducepd256_mask_round ((__v4df) __A, + __C, + (__v4df) + _mm256_setzero_pd (), + (__mmask8) -1, + __R); +} + +extern __inline __m256d +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_reduce_round_pd (__m256d __W, __mmask8 __U, __m256d __A, + const int __C, const int __R) +{ + return (__m256d) __builtin_ia32_reducepd256_mask_round ((__v4df) __A, + __C, + (__v4df) __W, + (__mmask8) __U, + __R); +} + +extern __inline __m256d +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_reduce_round_pd (__mmask8 __U, __m256d __A, const int __C, + const int __R) +{ + return (__m256d) __builtin_ia32_reducepd256_mask_round ((__v4df) __A, + __C, + (__v4df) + _mm256_setzero_pd (), + (__mmask8) __U, + __R); +} + +extern __inline __m256h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_reduce_round_ph (__m256h __A, const int __C, const int __R) +{ + return (__m256h) __builtin_ia32_reduceph256_mask_round ((__v16hf) __A, + __C, + (__v16hf) + _mm256_setzero_ph (), + (__mmask16) -1, + __R); +} + +extern __inline __m256h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_reduce_round_ph (__m256h __W, __mmask16 __U, __m256h __A, + const int __C, const int __R) +{ + return (__m256h) __builtin_ia32_reduceph256_mask_round ((__v16hf) __A, + __C, + (__v16hf) __W, + (__mmask16) __U, + __R); +} + +extern __inline __m256h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_reduce_round_ph (__mmask16 __U, __m256h __A, const int __C, + const int __R) +{ + return (__m256h) __builtin_ia32_reduceph256_mask_round ((__v16hf) __A, + __C, + (__v16hf) + _mm256_setzero_ph (), + (__mmask16) __U, + __R); +} + +extern __inline __m256 +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_reduce_round_ps (__m256 __A, const int __C, const int __R) +{ + return (__m256) __builtin_ia32_reduceps256_mask_round ((__v8sf) __A, + __C, + (__v8sf) + _mm256_setzero_ps (), + (__mmask8) -1, + __R); +} + +extern __inline __m256 +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_reduce_round_ps (__m256 __W, __mmask8 __U, __m256 __A, + const int __C, const int __R) +{ + return (__m256) __builtin_ia32_reduceps256_mask_round ((__v8sf) __A, + __C, + (__v8sf) __W, + (__mmask8) __U, + __R); +} + +extern __inline __m256 +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_reduce_round_ps (__mmask8 __U, __m256 __A, const int __C, + const int __R) +{ + return (__m256) __builtin_ia32_reduceps256_mask_round ((__v8sf) __A, + __C, + (__v8sf) + _mm256_setzero_ps (), + (__mmask8) __U, + __R); +} + +extern __inline __m256d +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_roundscale_round_pd (__m256d __A, const int __C, const int __R) +{ + return + (__m256d) __builtin_ia32_rndscalepd256_mask_round ((__v4df) __A, + __C, + (__v4df) + _mm256_undefined_pd (), + (__mmask8) -1, + __R); +} + +extern __inline __m256d +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_roundscale_round_pd (__m256d __W, __mmask8 __U, __m256d __A, + const int __C, const int __R) +{ + return (__m256d) __builtin_ia32_rndscalepd256_mask_round ((__v4df) __A, + __C, + (__v4df) __W, + (__mmask8) __U, + __R); +} + +extern __inline __m256d +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_roundscale_round_pd (__mmask8 __U, __m256d __A, const int __C, + const int __R) +{ + return + (__m256d) __builtin_ia32_rndscalepd256_mask_round ((__v4df) __A, + __C, + (__v4df) + _mm256_setzero_pd (), + (__mmask8) __U, + __R); +} + +extern __inline __m256h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_roundscale_round_ph (__m256h __A, const int __C, const int __R) +{ + return + (__m256h) __builtin_ia32_rndscaleph256_mask_round ((__v16hf) __A, + __C, + (__v16hf) + _mm256_undefined_ph (), + (__mmask16) -1, + __R); +} + +extern __inline __m256h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_roundscale_round_ph (__m256h __W, __mmask16 __U, __m256h __A, + const int __C, const int __R) +{ + return (__m256h) __builtin_ia32_rndscaleph256_mask_round ((__v16hf) __A, + __C, + (__v16hf) __W, + (__mmask16) __U, + __R); +} + +extern __inline __m256h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_roundscale_round_ph (__mmask16 __U, __m256h __A, const int __C, + const int __R) +{ + return + (__m256h) __builtin_ia32_rndscaleph256_mask_round ((__v16hf) __A, + __C, + (__v16hf) + _mm256_setzero_ph (), + (__mmask16) __U, + __R); +} + +extern __inline __m256 +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_roundscale_round_ps (__m256 __A, const int __C, const int __R) +{ + return + (__m256) __builtin_ia32_rndscaleps256_mask_round ((__v8sf) __A, + __C, + (__v8sf) + _mm256_undefined_ps (), + (__mmask8) -1, + __R); +} + +extern __inline __m256 +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_roundscale_round_ps (__m256 __W, __mmask8 __U, __m256 __A, + const int __C, const int __R) +{ + return (__m256) __builtin_ia32_rndscaleps256_mask_round ((__v8sf) __A, + __C, + (__v8sf) __W, + (__mmask8) __U, + __R); +} + +extern __inline __m256 +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_roundscale_round_ps (__mmask8 __U, __m256 __A, const int __C, + const int __R) +{ + return (__m256) __builtin_ia32_rndscaleps256_mask_round ((__v8sf) __A, + __C, + (__v8sf) + _mm256_setzero_ps (), + (__mmask8) __U, + __R); +} #else #define _mm256_add_round_pd(A, B, R) \ ((__m256d) __builtin_ia32_addpd256_mask_round ((__v4df) (A), \ @@ -5523,6 +5750,146 @@ _mm256_maskz_range_round_ps (__mmask8 __U, __m256 __A, __m256 __B, (_mm256_setzero_ps ()), \ (__mmask8) (U), \ (R))) + +#define _mm256_reduce_round_pd(A, C, R) \ + ((__m256d) __builtin_ia32_reducepd256_mask_round ((__v4df) (A), \ + (C), \ + (__v4df) \ + (_mm256_setzero_pd ()), \ + (__mmask8) (-1), \ + (R))) + +#define _mm256_mask_reduce_round_pd(W, U, A, C, R) \ + ((__m256d) __builtin_ia32_reducepd256_mask_round ((__v4df) (A), \ + (C), \ + (__v4df) (W), \ + (__mmask8) (U), \ + (R))) + +#define _mm256_maskz_reduce_round_pd(U, A, C, R) \ + ((__m256d) __builtin_ia32_reducepd256_mask_round ((__v4df) (A), \ + (C), \ + (__v4df) \ + (_mm256_setzero_pd ()), \ + (__mmask8) (U), \ + (R))) + +#define _mm256_reduce_round_ph(A, C, R) \ + ((__m256h) __builtin_ia32_reduceph256_mask_round ((__v16hf) (A), \ + (C), \ + (__v16hf) \ + (_mm256_setzero_ph ()), \ + (__mmask16) (-1), \ + (R))) + +#define _mm256_mask_reduce_round_ph(W, U, A, C, R) \ + ((__m256h) __builtin_ia32_reduceph256_mask_round ((__v16hf) (A), \ + (C), \ + (__v16hf) (W), \ + (__mmask16) (U), \ + (R))) + +#define _mm256_maskz_reduce_round_ph(U, A, C, R) \ + ((__m256h) __builtin_ia32_reduceph256_mask_round ((__v16hf) (A), \ + (C), \ + (__v16hf) \ + (_mm256_setzero_ph ()), \ + (__mmask16) (U), \ + (R))) + +#define _mm256_reduce_round_ps(A, C, R) \ + ((__m256) __builtin_ia32_reduceps256_mask_round ((__v8sf) (A), \ + (C), \ + (__v8sf) \ + (_mm256_setzero_ps ()), \ + (__mmask8) (-1), \ + (R))) + +#define _mm256_mask_reduce_round_ps(W, U, A, C, R) \ + ((__m256) __builtin_ia32_reduceps256_mask_round ((__v8sf) (A), \ + (C), \ + (__v8sf) (W), \ + (__mmask8) (U), \ + (R))) + +#define _mm256_maskz_reduce_round_ps(U, A, C, R) \ + ((__m256) __builtin_ia32_reduceps256_mask_round ((__v8sf) (A), \ + (C), \ + (__v8sf) \ + (_mm256_setzero_ps ()), \ + (__mmask8) (U), \ + (R))) + +#define _mm256_roundscale_round_pd(A, C, R) \ + ((__m256d) \ + __builtin_ia32_rndscalepd256_mask_round ((__v4df) (A), \ + (C), \ + (__v4df) \ + (_mm256_undefined_pd ()), \ + (__mmask8) (-1), \ + (R))) + +#define _mm256_mask_roundscale_round_pd(W, U, A, C, R) \ + ((__m256d) __builtin_ia32_rndscalepd256_mask_round ((__v4df) (A), \ + (C), \ + (__v4df) (W), \ + (__mmask8) (U), \ + (R))) + +#define _mm256_maskz_roundscale_round_pd(U, A, C, R) \ + ((__m256d) __builtin_ia32_rndscalepd256_mask_round ((__v4df) (A), \ + (C), \ + (__v4df) \ + (_mm256_setzero_pd ()), \ + (__mmask8) (U), \ + (R))) + +#define _mm256_roundscale_round_ph(A, C, R) \ + ((__m256h) \ + __builtin_ia32_rndscaleph256_mask_round ((__v16hf) (A), \ + (C), \ + (__v16hf) \ + (_mm256_undefined_ph ()), \ + (__mmask16) (-1), \ + (R))) + +#define _mm256_mask_roundscale_round_ph(W, U, A, C, R) \ + ((__m256h) __builtin_ia32_rndscaleph256_mask_round ((__v16hf) (A), \ + (C), \ + (__v16hf) (W), \ + (__mmask16) (U), \ + (R))) + +#define _mm256_maskz_roundscale_round_ph(U, A, C, R) \ + ((__m256h) __builtin_ia32_rndscaleph256_mask_round ((__v16hf) (A), \ + (C), \ + (__v16hf) \ + (_mm256_setzero_ph ()), \ + (__mmask16) (U), \ + (R))) + +#define _mm256_roundscale_round_ps(A, C, R) \ + ((__m256) __builtin_ia32_rndscaleps256_mask_round ((__v8sf) (A), \ + (C), \ + (__v8sf) \ + (_mm256_undefined_ps ()), \ + (__mmask8) (-1), \ + (R))) + +#define _mm256_mask_roundscale_round_ps(W, U, A, C, R) \ + ((__m256) __builtin_ia32_rndscaleps256_mask_round ((__v8sf) (A), \ + (C), \ + (__v8sf) (W), \ + (__mmask8) (U), \ + (R))) + +#define _mm256_maskz_roundscale_round_ps(U, A, C, R) \ + ((__m256) __builtin_ia32_rndscaleps256_mask_round ((__v8sf) (A), \ + (C), \ + (__v8sf) \ + (_mm256_setzero_ps ()), \ + (__mmask8) (U), \ + (R))) #endif #define _mm256_cmul_round_pch(A, B, R) _mm256_fcmul_round_pch ((A), (B), (R)) diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index 232ec53f4f8..2b9acfa50ce 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -3462,6 +3462,12 @@ BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_mulv16hf3_mask_round, "__builti BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_mulv8sf3_mask_round, "__builtin_ia32_mulps256_mask_round", IX86_BUILTIN_VMULPS256_MASK_ROUND, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI_INT) BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512dq_rangepv4df_mask_round, "__builtin_ia32_rangepd256_mask_round", IX86_BUILTIN_VRANGEPD256_MASK_ROUND, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_UQI_INT) BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512dq_rangepv8sf_mask_round, "__builtin_ia32_rangeps256_mask_round", IX86_BUILTIN_VRANGEPS256_MASK_ROUND, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_UQI_INT) +BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_reducepv4df_mask_round, "__builtin_ia32_reducepd256_mask_round", IX86_BUILTIN_VREDUCEPD256_MASK_ROUND, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_UQI_INT) +BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_reducepv16hf_mask_round, "__builtin_ia32_reduceph256_mask_round", IX86_BUILTIN_VREDUCEPH256_MASK_ROUND, UNKNOWN, (int) V16HF_FTYPE_V16HF_INT_V16HF_UHI_INT) +BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_reducepv8sf_mask_round, "__builtin_ia32_reduceps256_mask_round", IX86_BUILTIN_VREDUCEPS256_MASK_ROUND, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_UQI_INT) +BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_rndscalev4df_mask_round, "__builtin_ia32_rndscalepd256_mask_round", IX86_BUILTIN_VRNDSCALEPD256_MASK_ROUND, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_UQI_INT) +BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_rndscalev16hf_mask_round, "__builtin_ia32_rndscaleph256_mask_round", IX86_BUILTIN_VRNDSCALEPH256_MASK_ROUND, UNKNOWN, (int) V16HF_FTYPE_V16HF_INT_V16HF_UHI_INT) +BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_rndscalev8sf_mask_round, "__builtin_ia32_rndscaleps256_mask_round", IX86_BUILTIN_VRNDSCALEPS256_MASK_ROUND, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_UQI_INT) BDESC_END (ROUND_ARGS, MULTI_ARG) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 52de8194366..73a813454ca 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -3772,7 +3772,7 @@ [(match_operand:VFH_AVX512VL 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>") (match_operand:SI 2 "const_0_to_255_operand")] UNSPEC_REDUCE))] - "TARGET_AVX512DQ || (VALID_AVX512FP16_REG_MODE (<MODE>mode))" + "(TARGET_AVX512DQ || (VALID_AVX512FP16_REG_MODE (<MODE>mode))) && <round_saeonly_mode_condition>" "vreduce<ssemodesuffix>\t{%2, <round_saeonly_mask_op3>%1, %0<mask_operand3>|%0<mask_operand3>, %1<round_saeonly_mask_op3>, %2}" [(set_attr "type" "sse") (set_attr "prefix" "evex") @@ -13934,7 +13934,7 @@ [(match_operand:VFH_AVX512VL 1 "nonimmediate_operand" "<round_saeonly_constraint>") (match_operand:SI 2 "const_0_to_255_operand")] UNSPEC_ROUND))] - "TARGET_AVX512F" + "TARGET_AVX512F && <round_saeonly_mode_condition>" "vrndscale<ssemodesuffix>\t{%2, <round_saeonly_mask_op3>%1, %0<mask_operand3>|%0<mask_operand3>, %1<round_saeonly_mask_op3>, %2}" [(set_attr "length_immediate" "1") (set_attr "prefix" "evex") diff --git a/gcc/testsuite/gcc.target/i386/avx-1.c b/gcc/testsuite/gcc.target/i386/avx-1.c index 8d133f047d2..1b6cc87e0ef 100644 --- a/gcc/testsuite/gcc.target/i386/avx-1.c +++ b/gcc/testsuite/gcc.target/i386/avx-1.c @@ -986,6 +986,12 @@ #define __builtin_ia32_mulps256_mask_round(A, B, C, D, E) __builtin_ia32_mulps256_mask_round(A, B, C, D, 8) #define __builtin_ia32_rangeps256_mask_round(A, B, I, D, E, F) __builtin_ia32_rangeps256_mask_round(A, B, 1, D, E, 8) #define __builtin_ia32_rangepd256_mask_round(A, B, I, D, E, F) __builtin_ia32_rangepd256_mask_round(A, B, 1, D, E, 8) +#define __builtin_ia32_reducepd256_mask_round(A, B, C, D, E) __builtin_ia32_reducepd256_mask_round(A, 8, C, D, 8) +#define __builtin_ia32_reduceph256_mask_round(A, B, C, D, E) __builtin_ia32_reduceph256_mask_round(A, 8, C, D, 8) +#define __builtin_ia32_reduceps256_mask_round(A, B, C, D, E) __builtin_ia32_reduceps256_mask_round(A, 8, C, D, 8) +#define __builtin_ia32_rndscalepd256_mask_round(A, B, C, D, E) __builtin_ia32_rndscalepd256_mask_round(A, 1, C, D, 8) +#define __builtin_ia32_rndscaleph256_mask_round(A, B, C, D, E) __builtin_ia32_rndscaleph256_mask_round(A, 1, C, D, 8) +#define __builtin_ia32_rndscaleps256_mask_round(A, B, C, D, E) __builtin_ia32_rndscaleps256_mask_round(A, 1, C, D, 8) #include <wmmintrin.h> #include <immintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-rounding-3.c b/gcc/testsuite/gcc.target/i386/avx10_2-rounding-3.c index dd3e8be85fd..5d13ad90ac3 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-rounding-3.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-rounding-3.c @@ -156,6 +156,24 @@ /* { dg-final { scan-assembler-times "vrangeps\[ \\t\]+\[^\$\n\]*\\$\[^\{\n\]*\{sae\}\[^\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vrangeps\[ \\t\]+\[^\$\n\]*\\$\[^\{\n\]*\{sae\}\[^\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vrangeps\[ \\t\]+\[^\$\n\]*\\$\[^\{\n\]*\{sae\}\[^\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vreducepd\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vreducepd\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vreducepd\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vreduceph\[ \\t\]+\[^\{\n\]*\{sae\}\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vreduceph\[ \\t\]+\[^\{\n\]*\{sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vreduceph\[ \\t\]+\[^\{\n\]*\{sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vreduceps\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vreduceps\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vreduceps\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrndscalepd\[ \\t\]+\\S*,\[ \\t\]+\{sae\}\[^\n\]*%ymm\[0-9\]+\[^\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrndscalepd\[ \\t\]+\\S*,\[ \\t\]+\{sae\}\[^\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrndscalepd\[ \\t\]+\\S*,\[ \\t\]+\{sae\}\[^\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrndscaleph\[ \\t\]+\[^\n\]*\{sae\}\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrndscaleph\[ \\t\]+\[^\n\]*\{sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrndscaleph\[ \\t\]+\[^\n\]*\{sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrndscaleps\[ \\t\]+\\S*,\[ \\t\]+\{sae\}\[^\n\]*%ymm\[0-9\]+\[^\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrndscaleps\[ \\t\]+\\S*,\[ \\t\]+\{sae\}\[^\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrndscaleps\[ \\t\]+\\S*,\[ \\t\]+\{sae\}\[^\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ #include <immintrin.h> @@ -474,3 +492,35 @@ avx10_2_test_21 (void) x = _mm256_mask_range_round_ps (x, m16, x, x, 15, _MM_FROUND_NO_EXC); x = _mm256_maskz_range_round_ps (m16, x, x, 15, _MM_FROUND_NO_EXC); } + +void extern +avx10_2_test_22 (void) +{ + xd = _mm256_reduce_round_pd (xd, 123, _MM_FROUND_NO_EXC); + xd = _mm256_mask_reduce_round_pd (xd, m8, xd, 123, _MM_FROUND_NO_EXC); + xd = _mm256_maskz_reduce_round_pd (m8, xd, 123, _MM_FROUND_NO_EXC); + + xh = _mm256_reduce_round_ph (xh, 123, _MM_FROUND_NO_EXC); + xh = _mm256_mask_reduce_round_ph (xh, m16, xh, 123, _MM_FROUND_NO_EXC); + xh = _mm256_maskz_reduce_round_ph (m16, xh, 123, _MM_FROUND_NO_EXC); + + x = _mm256_reduce_round_ps (x, 123, _MM_FROUND_NO_EXC); + x = _mm256_mask_reduce_round_ps (x, m8, x, 123, _MM_FROUND_NO_EXC); + x = _mm256_maskz_reduce_round_ps (m8, x, 123, _MM_FROUND_NO_EXC); +} + +void extern +avx10_2_test_23 (void) +{ + xd = _mm256_roundscale_round_pd (xd, 0x42, _MM_FROUND_NO_EXC); + xd = _mm256_mask_roundscale_round_pd (xd, 2, xd, 0x42, _MM_FROUND_NO_EXC); + xd = _mm256_maskz_roundscale_round_pd (2, xd, 0x42, _MM_FROUND_NO_EXC); + + xh = _mm256_roundscale_round_ph (xh, 123, 8); + xh = _mm256_mask_roundscale_round_ph (xh, m16, xh, 123, 8); + xh = _mm256_maskz_roundscale_round_ph (m16, xh, 123, 8); + + x = _mm256_roundscale_round_ps (x, 0x42, _MM_FROUND_NO_EXC); + x = _mm256_mask_roundscale_round_ps (x, 2, x, 0x42, _MM_FROUND_NO_EXC); + x = _mm256_maskz_roundscale_round_ps (2, x, 0x42, _MM_FROUND_NO_EXC); +} diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c index 95005c311ac..d15802310d9 100644 --- a/gcc/testsuite/gcc.target/i386/sse-13.c +++ b/gcc/testsuite/gcc.target/i386/sse-13.c @@ -993,5 +993,11 @@ #define __builtin_ia32_mulps256_mask_round(A, B, C, D, E) __builtin_ia32_mulps256_mask_round(A, B, C, D, 8) #define __builtin_ia32_rangeps256_mask_round(A, B, C, D, E, F) __builtin_ia32_rangeps256_mask_round(A, B, 1, D, E, 8) #define __builtin_ia32_rangepd256_mask_round(A, B, C, D, E, F) __builtin_ia32_rangepd256_mask_round(A, B, 1, D, E, 8) +#define __builtin_ia32_reducepd256_mask_round(A, B, C, D, E) __builtin_ia32_reducepd256_mask_round(A, 8, C, D, 8) +#define __builtin_ia32_reduceph256_mask_round(A, B, C, D, E) __builtin_ia32_reduceph256_mask_round(A, 8, C, D, 8) +#define __builtin_ia32_reduceps256_mask_round(A, B, C, D, E) __builtin_ia32_reduceps256_mask_round(A, 8, C, D, 8) +#define __builtin_ia32_rndscalepd256_mask_round(A, B, C, D, E) __builtin_ia32_rndscalepd256_mask_round(A, 1, C, D, 8) +#define __builtin_ia32_rndscaleph256_mask_round(A, B, C, D, E) __builtin_ia32_rndscaleph256_mask_round(A, 1, C, D, 8) +#define __builtin_ia32_rndscaleps256_mask_round(A, B, C, D, E) __builtin_ia32_rndscaleps256_mask_round(A, 1, C, D, 8) #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc/testsuite/gcc.target/i386/sse-14.c index 9e61ef99b3c..f69172955cf 100644 --- a/gcc/testsuite/gcc.target/i386/sse-14.c +++ b/gcc/testsuite/gcc.target/i386/sse-14.c @@ -1069,6 +1069,12 @@ test_1 (_mm256_cvt_roundepi16_ph, __m256h, __m256i, 8) test_1 (_mm256_getexp_round_pd, __m256d, __m256d, 8) test_1 (_mm256_getexp_round_ph, __m256h, __m256h, 8) test_1 (_mm256_getexp_round_ps, __m256, __m256, 8) +test_1x (_mm256_reduce_round_ph, __m256h, __m256h, 123, 8) +test_1x (_mm256_reduce_round_ps, __m256, __m256, 123, 8) +test_1x (_mm256_reduce_round_pd, __m256d, __m256d, 123, 8) +test_1x (_mm256_roundscale_round_ph, __m256h, __m256h, 123, 8) +test_1x (_mm256_roundscale_round_ps, __m256, __m256, 123, 8) +test_1x (_mm256_roundscale_round_pd, __m256d, __m256d, 123, 8) test_1y (_mm256_getmant_round_ph, __m256h, __m256h, 1, 1, 8) test_1y (_mm256_getmant_round_ps, __m256, __m256, 1, 1, 8) test_1y (_mm256_getmant_round_pd, __m256d, __m256d, 1, 1, 8) @@ -1143,6 +1149,12 @@ test_2x (_mm256_cmp_round_ph_mask, __mmask16, __m256h, __m256h, 1, 8) test_2x (_mm256_cmp_round_ps_mask, __mmask8, __m256, __m256, 1, 8) test_2x (_mm256_range_round_pd, __m256d, __m256d, __m256d, 15, 8) test_2x (_mm256_range_round_ps, __m256, __m256, __m256, 15, 8) +test_2x (_mm256_maskz_reduce_round_pd, __m256d, __mmask8, __m256d, 123, 8) +test_2x (_mm256_maskz_reduce_round_ph, __m256h, __mmask8, __m256h, 123, 8) +test_2x (_mm256_maskz_reduce_round_ps, __m256, __mmask16, __m256, 123, 8) +test_2x (_mm256_maskz_roundscale_round_pd, __m256d, __mmask8, __m256d, 123, 8) +test_2x (_mm256_maskz_roundscale_round_ph, __m256h, __mmask8, __m256h, 123, 8) +test_2x (_mm256_maskz_roundscale_round_ps, __m256, __mmask16, __m256, 123, 8) test_2y (_mm256_maskz_getmant_round_pd, __m256d, __mmask8, __m256d, 1, 1, 8) test_2y (_mm256_maskz_getmant_round_ph, __m256h, __mmask16, __m256h, 1, 1, 8) test_2y (_mm256_maskz_getmant_round_ps, __m256, __mmask8, __m256, 1, 1, 8) @@ -1240,6 +1252,12 @@ test_3x (_mm256_fixupimm_round_pd, __m256d, __m256d, __m256d, __m256i, 3, 8) test_3x (_mm256_fixupimm_round_ps, __m256, __m256, __m256, __m256i, 3, 8) test_3x (_mm256_maskz_range_round_pd, __m256d, __mmask8, __m256d, __m256d, 15, 8) test_3x (_mm256_maskz_range_round_ps, __m256, __mmask8, __m256, __m256, 15, 8) +test_3x (_mm256_mask_reduce_round_ph, __m256h, __m256h, __mmask8, __m256h, 123, 8) +test_3x (_mm256_mask_reduce_round_ps, __m256, __m256, __mmask16, __m256, 123, 8) +test_3x (_mm256_mask_reduce_round_pd, __m256d, __m256d, __mmask8, __m256d, 123, 8) +test_3x (_mm256_mask_roundscale_round_ph, __m256h, __m256h, __mmask8, __m256h, 123, 8) +test_3x (_mm256_mask_roundscale_round_ps, __m256, __m256, __mmask16, __m256, 123, 8) +test_3x (_mm256_mask_roundscale_round_pd, __m256d, __m256d, __mmask8, __m256d, 123, 8) test_3y (_mm256_mask_getmant_round_pd, __m256d, __m256d, __mmask8, __m256d, 1, 1, 8) test_3y (_mm256_mask_getmant_round_ph, __m256h, __m256h, __mmask16, __m256h, 1, 1, 8) test_3y (_mm256_mask_getmant_round_ps, __m256, __m256, __mmask8, __m256, 1, 1, 8) diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc/testsuite/gcc.target/i386/sse-22.c index cc37230fa01..767a7df1e07 100644 --- a/gcc/testsuite/gcc.target/i386/sse-22.c +++ b/gcc/testsuite/gcc.target/i386/sse-22.c @@ -1112,6 +1112,12 @@ test_1 (_mm256_cvt_roundepi16_ph, __m256h, __m256i, 8) test_1 (_mm256_getexp_round_pd, __m256d, __m256d, 8) test_1 (_mm256_getexp_round_ph, __m256h, __m256h, 8) test_1 (_mm256_getexp_round_ps, __m256, __m256, 8) +test_1x (_mm256_reduce_round_ph, __m256h, __m256h, 123, 8) +test_1x (_mm256_reduce_round_ps, __m256, __m256, 123, 8) +test_1x (_mm256_reduce_round_pd, __m256d, __m256d, 123, 8) +test_1x (_mm256_roundscale_round_ph, __m256h, __m256h, 123, 8) +test_1x (_mm256_roundscale_round_ps, __m256, __m256, 123, 8) +test_1x (_mm256_roundscale_round_pd, __m256d, __m256d, 123, 8) test_1y (_mm256_getmant_round_ph, __m256h, __m256h, 1, 1, 8) test_1y (_mm256_getmant_round_ps, __m256, __m256, 1, 1, 8) test_1y (_mm256_getmant_round_pd, __m256d, __m256d, 1, 1, 8) @@ -1186,6 +1192,12 @@ test_2x (_mm256_cmp_round_ph_mask, __mmask16, __m256h, __m256h, 1, 8) test_2x (_mm256_cmp_round_ps_mask, __mmask8, __m256, __m256, 1, 8) test_2x (_mm256_range_round_pd, __m256d, __m256d, __m256d, 15, 8) test_2x (_mm256_range_round_ps, __m256, __m256, __m256, 15, 8) +test_2x (_mm256_maskz_reduce_round_pd, __m256d, __mmask8, __m256d, 123, 8) +test_2x (_mm256_maskz_reduce_round_ph, __m256h, __mmask8, __m256h, 123, 8) +test_2x (_mm256_maskz_reduce_round_ps, __m256, __mmask16, __m256, 123, 8) +test_2x (_mm256_maskz_roundscale_round_pd, __m256d, __mmask8, __m256d, 123, 8) +test_2x (_mm256_maskz_roundscale_round_ph, __m256h, __mmask8, __m256h, 123, 8) +test_2x (_mm256_maskz_roundscale_round_ps, __m256, __mmask16, __m256, 123, 8) test_2y (_mm256_maskz_getmant_round_pd, __m256d, __mmask8, __m256d, 1, 1, 8) test_2y (_mm256_maskz_getmant_round_ph, __m256h, __mmask16, __m256h, 1, 1, 8) test_2y (_mm256_maskz_getmant_round_ps, __m256, __mmask8, __m256, 1, 1, 8) @@ -1282,6 +1294,12 @@ test_3x (_mm256_fixupimm_round_pd, __m256d, __m256d, __m256d, __m256i, 3, 8) test_3x (_mm256_fixupimm_round_ps, __m256, __m256, __m256, __m256i, 3, 8) test_3x (_mm256_maskz_range_round_pd, __m256d, __mmask8, __m256d, __m256d, 15, 8) test_3x (_mm256_maskz_range_round_ps, __m256, __mmask16, __m256, __m256, 15, 8) +test_3x (_mm256_mask_reduce_round_ph, __m256h, __m256h, __mmask8, __m256h, 123, 8) +test_3x (_mm256_mask_reduce_round_ps, __m256, __m256, __mmask16, __m256, 123, 8) +test_3x (_mm256_mask_reduce_round_pd, __m256d, __m256d, __mmask8, __m256d, 123, 8) +test_3x (_mm256_mask_roundscale_round_ph, __m256h, __m256h, __mmask8, __m256h, 123, 8) +test_3x (_mm256_mask_roundscale_round_ps, __m256, __m256, __mmask16, __m256, 123, 8) +test_3x (_mm256_mask_roundscale_round_pd, __m256d, __m256d, __mmask8, __m256d, 123, 8) test_3y (_mm256_mask_getmant_round_pd, __m256d, __m256d, __mmask8, __m256d, 1, 1, 8) test_3y (_mm256_mask_getmant_round_ph, __m256h, __m256h, __mmask16, __m256h, 1, 1, 8) test_3y (_mm256_mask_getmant_round_ps, __m256, __m256, __mmask8, __m256, 1, 1, 8) diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c index bb418a74d25..8c065feaa16 100644 --- a/gcc/testsuite/gcc.target/i386/sse-23.c +++ b/gcc/testsuite/gcc.target/i386/sse-23.c @@ -968,6 +968,12 @@ #define __builtin_ia32_mulps256_mask_round(A, B, C, D, E) __builtin_ia32_mulps256_mask_round(A, B, C, D, 8) #define __builtin_ia32_rangeps256_mask_round(A, B, C, D, E, F) __builtin_ia32_rangeps256_mask_round(A, B, 1, D, E, 8) #define __builtin_ia32_rangepd256_mask_round(A, B, C, D, E, F) __builtin_ia32_rangepd256_mask_round(A, B, 1, D, E, 8) +#define __builtin_ia32_reducepd256_mask_round(A, B, C, D, E) __builtin_ia32_reducepd256_mask_round(A, 8, C, D, 8) +#define __builtin_ia32_reduceph256_mask_round(A, B, C, D, E) __builtin_ia32_reduceph256_mask_round(A, 8, C, D, 8) +#define __builtin_ia32_reduceps256_mask_round(A, B, C, D, E) __builtin_ia32_reduceps256_mask_round(A, 8, C, D, 8) +#define __builtin_ia32_rndscalepd256_mask_round(A, B, C, D, E) __builtin_ia32_rndscalepd256_mask_round(A, 1, C, D, 8) +#define __builtin_ia32_rndscaleph256_mask_round(A, B, C, D, E) __builtin_ia32_rndscaleph256_mask_round(A, 1, C, D, 8) +#define __builtin_ia32_rndscaleps256_mask_round(A, B, C, D, E) __builtin_ia32_rndscaleps256_mask_round(A, 1, C, D, 8) #pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,sha,xsavec,xsaves,clflushopt,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,vpclmulqdq,pconfig,wbnoinvd,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2-512")

[20/22] AVX10.2 ymm rounding: Support vreducep{s, d, h} and vrndscalep{s, d, h} intrins

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Patch