From patchwork Wed Aug 14 09:01:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haochen Jiang X-Patchwork-Id: 1972254 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=lVdxKdmp; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4WkMm10s1Yz1yfZ for ; Wed, 14 Aug 2024 19:05:21 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 40FC7385DDE9 for ; Wed, 14 Aug 2024 09:05:18 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by sourceware.org (Postfix) with ESMTPS id 4B092385B505 for ; Wed, 14 Aug 2024 09:04:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4B092385B505 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 4B092385B505 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1723626266; cv=none; b=jJd6HbCKl1OqO0tXl/vMKmptgnwZdPAMZedOwGAyCxFKSiHC9pnE76e6fseg4fTWClxbzvg+dhP6DEQgR24UIvykdGv7Og5Gyik/xz453t3ErIQAWBb0eO9wquU/1y4DPOgsd+RFSBMKrZ1vc5SPWhQuLV4guYwh75HcCl2xJ/A= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1723626266; c=relaxed/simple; bh=BYR2BTc98wA70fuC4Q4CcVC7QnRFCaPQzF4gdeutJgM=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=IXFlqTrBMJKNUxzr0B/0dceVPbuFnJcMSsa0dHwYqVDRsDkXinj4W3u8uX2M3s3AQOBvUyKoEHMHK6vLqHdEpeLVU/z9+XvlTErAacxyBzOwgEbiI7U/cP2UM7DubOx+lcMdnFtareMUSgdwRxljOMxTaNAA8Jl6mI9FyM+Btp0= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1723626252; x=1755162252; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BYR2BTc98wA70fuC4Q4CcVC7QnRFCaPQzF4gdeutJgM=; b=lVdxKdmp2awekc0OaV3B0AuwzocpYzvVOwVnyJRtZkohrVmKCp4w/TnO 1HIPtZhifBCcZqlQyoYpVpbd+LtkcJl2XMT+raW7vpreY5IbKd5+6sejk khaAk7+dxwqbGl5+N281Nb3jQgxsul50LjXHo4U5dYsV3D0kDTHAQEjfP W94jLJ3eZVeOJRUpIVLTsForid1k2QFVXSsr8eZuR3v4ReQqqMAp5g+Bz ZE34/+3zBjQBzVy83O0KwggTXOSH0mCD5HqL675mZROaAdjBIZDjhf5cY umwrEU5h3Mn3B3zOXv9WVRdhHiMUrllaJ/0wKUFujZUMrYiKY08GveCuj g==; X-CSE-ConnectionGUID: JOjmahJLQS+BazFxtVTDcw== X-CSE-MsgGUID: ndPsttyERB+LkPqA3Svsrg== X-IronPort-AV: E=McAfee;i="6700,10204,11163"; a="44349169" X-IronPort-AV: E=Sophos;i="6.09,288,1716274800"; d="scan'208";a="44349169" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2024 02:04:10 -0700 X-CSE-ConnectionGUID: uxCnO59yQF6SMmkiv+3HGQ== X-CSE-MsgGUID: +DHvf+VhRK+yj56PuKRRAw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,288,1716274800"; d="scan'208";a="59519168" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orviesa007.jf.intel.com with ESMTP; 14 Aug 2024 02:04:07 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 6E90C100734D; Wed, 14 Aug 2024 17:04:01 +0800 (CST) From: Haochen Jiang To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com, ubizjak@gmail.com, "Hu, Lin1" Subject: [PATCH 12/22] AVX10.2 ymm rounding: Support vfmadd{132, 231, 213}p{s, d, h} intrins Date: Wed, 14 Aug 2024 17:01:49 +0800 Message-Id: <20240814090159.422097-13-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20240814090159.422097-1-haochen.jiang@intel.com> References: <20240814090159.422097-1-haochen.jiang@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: "Hu, Lin1" gcc/ChangeLog: * config/i386/avx10_2roundingintrin.h: New intrins. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/sse.md: (_fmadd__mask3): Add condition check. gcc/testsuite/ChangeLog: * gcc.target/i386/avx-1.c: Add new builtin test. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add new macro test. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/avx10_2-rounding-3.c: New test. --- gcc/config/i386/avx10_2roundingintrin.h | 176 ++++++++++++++++++ gcc/config/i386/i386-builtin.def | 9 + gcc/config/i386/sse.md | 2 +- gcc/testsuite/gcc.target/i386/avx-1.c | 9 + .../gcc.target/i386/avx10_2-rounding-3.c | 31 +++ gcc/testsuite/gcc.target/i386/sse-13.c | 9 + gcc/testsuite/gcc.target/i386/sse-14.c | 12 ++ gcc/testsuite/gcc.target/i386/sse-22.c | 12 ++ gcc/testsuite/gcc.target/i386/sse-23.c | 9 + 9 files changed, 268 insertions(+), 1 deletion(-) diff --git a/gcc/config/i386/avx10_2roundingintrin.h b/gcc/config/i386/avx10_2roundingintrin.h index d5ea6bc57da..9015095144e 100644 --- a/gcc/config/i386/avx10_2roundingintrin.h +++ b/gcc/config/i386/avx10_2roundingintrin.h @@ -2092,6 +2092,146 @@ _mm256_maskz_fixupimm_round_ps (__mmask8 __U, __m256 __A, __m256 __B, (__mmask8) __U, __R); } + +extern __inline __m256d +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_fmadd_round_pd (__m256d __A, __m256d __B, __m256d __D, const int __R) +{ + return (__m256d) __builtin_ia32_vfmaddpd256_mask_round ((__v4df) __A, + (__v4df) __B, + (__v4df) __D, + (__mmask8) -1, + __R); +} + +extern __inline __m256d +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_fmadd_round_pd (__m256d __A, __mmask8 __U, __m256d __B, + __m256d __D, const int __R) +{ + return (__m256d) __builtin_ia32_vfmaddpd256_mask_round ((__v4df) __A, + (__v4df) __B, + (__v4df) __D, + (__mmask8) __U, __R); +} + +extern __inline __m256d +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask3_fmadd_round_pd (__m256d __A, __m256d __B, __m256d __D, + __mmask8 __U, const int __R) +{ + return (__m256d) __builtin_ia32_vfmaddpd256_mask3_round ((__v4df) __A, + (__v4df) __B, + (__v4df) __D, + (__mmask8) __U, + __R); +} + +extern __inline __m256d +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_fmadd_round_pd (__mmask8 __U, __m256d __A, __m256d __B, + __m256d __D, const int __R) +{ + return (__m256d) __builtin_ia32_vfmaddpd256_maskz_round ((__v4df) __A, + (__v4df) __B, + (__v4df) __D, + (__mmask8) __U, + __R); +} + +extern __inline __m256h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_fmadd_round_ph (__m256h __A, __m256h __B, __m256h __D, const int __R) +{ + return (__m256h) __builtin_ia32_vfmaddph256_mask_round ((__v16hf) __A, + (__v16hf) __B, + (__v16hf) __D, + (__mmask16) -1, + __R); +} + +extern __inline __m256h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_fmadd_round_ph (__m256h __A, __mmask16 __U, __m256h __B, + __m256h __D, const int __R) +{ + return (__m256h) __builtin_ia32_vfmaddph256_mask_round ((__v16hf) __A, + (__v16hf) __B, + (__v16hf) __D, + (__mmask16) __U, + __R); +} + +extern __inline __m256h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask3_fmadd_round_ph (__m256h __A, __m256h __B, __m256h __D, + __mmask16 __U, const int __R) +{ + return (__m256h) __builtin_ia32_vfmaddph256_mask3_round ((__v16hf) __A, + (__v16hf) __B, + (__v16hf) __D, + (__mmask16) __U, + __R); +} + +extern __inline __m256h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_fmadd_round_ph (__mmask16 __U, __m256h __A, __m256h __B, + __m256h __D, const int __R) +{ + return (__m256h) __builtin_ia32_vfmaddph256_maskz_round ((__v16hf) __A, + (__v16hf) __B, + (__v16hf) __D, + (__mmask16) __U, + __R); +} + +extern __inline __m256 +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_fmadd_round_ps (__m256 __A, __m256 __B, __m256 __D, const int __R) +{ + return (__m256) __builtin_ia32_vfmaddps256_mask_round ((__v8sf) __A, + (__v8sf) __B, + (__v8sf) __D, + (__mmask8) -1, + __R); +} + +extern __inline __m256 +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_fmadd_round_ps (__m256 __A, __mmask8 __U, __m256 __B, + __m256 __D, const int __R) +{ + return (__m256) __builtin_ia32_vfmaddps256_mask_round ((__v8sf) __A, + (__v8sf) __B, + (__v8sf) __D, + (__mmask8) __U, + __R); +} + +extern __inline __m256 +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask3_fmadd_round_ps (__m256 __A, __m256 __B, __m256 __D, + __mmask8 __U, const int __R) +{ + return (__m256) __builtin_ia32_vfmaddps256_mask3_round ((__v8sf) __A, + (__v8sf) __B, + (__v8sf) __D, + (__mmask8) __U, + __R); +} + +extern __inline __m256 +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_fmadd_round_ps (__mmask8 __U, __m256 __A, __m256 __B, + __m256 __D, const int __R) +{ + return (__m256) __builtin_ia32_vfmaddps256_maskz_round ((__v8sf) __A, + (__v8sf) __B, + (__v8sf) __D, + (__mmask8) __U, + __R); +} #else #define _mm256_add_round_pd(A, B, R) \ ((__m256d) __builtin_ia32_addpd256_mask_round ((__v4df) (A), \ @@ -3329,6 +3469,42 @@ _mm256_maskz_fixupimm_round_ps (__mmask8 __U, __m256 __A, __m256 __B, (C), \ (__mmask8) (U), \ (R))) + +#define _mm256_fmadd_round_pd(A, B, D, R) \ + ((__m256d) __builtin_ia32_vfmaddpd256_mask_round (A, B, D, -1, R)) + +#define _mm256_mask_fmadd_round_pd(A, U, B, D, R) \ + ((__m256d) __builtin_ia32_vfmaddpd256_mask_round (A, B, D, U, R)) + +#define _mm256_mask3_fmadd_round_pd(A, B, D, U, R) \ + ((__m256d) __builtin_ia32_vfmaddpd256_mask3_round (A, B, D, U, R)) + +#define _mm256_maskz_fmadd_round_pd(U, A, B, D, R) \ + ((__m256d) __builtin_ia32_vfmaddpd256_maskz_round (A, B, D, U, R)) + +#define _mm256_fmadd_round_ph(A, B, D, R) \ + ((__m256h) __builtin_ia32_vfmaddph256_mask_round (A, B, D, -1, R)) + +#define _mm256_mask_fmadd_round_ph(A, U, B, D, R) \ + ((__m256h) __builtin_ia32_vfmaddph256_mask_round (A, B, D, U, R)) + +#define _mm256_mask3_fmadd_round_ph(A, B, D, U, R) \ + ((__m256h) __builtin_ia32_vfmaddph256_mask3_round (A, B, D, U, R)) + +#define _mm256_maskz_fmadd_round_ph(U, A, B, D, R) \ + ((__m256h) __builtin_ia32_vfmaddph256_maskz_round (A, B, D, U, R)) + +#define _mm256_fmadd_round_ps(A, B, D, R) \ + ((__m256)__builtin_ia32_vfmaddps256_mask_round (A, B, D, -1, R)) + +#define _mm256_mask_fmadd_round_ps(A, U, B, D, R) \ + ((__m256)__builtin_ia32_vfmaddps256_mask_round (A, B, D, U, R)) + +#define _mm256_mask3_fmadd_round_ps(A, B, D, U, R) \ + ((__m256)__builtin_ia32_vfmaddps256_mask3_round (A, B, D, U, R)) + +#define _mm256_maskz_fmadd_round_ps(U, A, B, D, R) \ + ((__m256)__builtin_ia32_vfmaddps256_maskz_round (A, B, D, U, R)) #endif #define _mm256_cmul_round_pch(A, B, R) _mm256_fcmul_round_pch ((A), (B), (R)) diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index 55a644a67bb..33e7573503f 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -3385,6 +3385,15 @@ BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fixupimmv4df_mask_roun BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fixupimmv4df_maskz_round, "__builtin_ia32_fixupimmpd256_maskz_round", IX86_BUILTIN_VFIXUPIMMPD256_MASKZ_ROUND, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_UQI_INT) BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fixupimmv8sf_mask_round, "__builtin_ia32_fixupimmps256_mask_round", IX86_BUILTIN_VFIXUPIMMPS256_MASK_ROUND, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_UQI_INT) BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fixupimmv8sf_maskz_round, "__builtin_ia32_fixupimmps256_maskz_round", IX86_BUILTIN_VFIXUPIMMPS256_MASKZ_ROUND, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_UQI_INT) +BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fmadd_v4df_mask_round, "__builtin_ia32_vfmaddpd256_mask_round", IX86_BUILTIN_VFMADDPD256_MASK_ROUND, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI_INT) +BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fmadd_v4df_mask3_round, "__builtin_ia32_vfmaddpd256_mask3_round", IX86_BUILTIN_VFMADDPD256_MASK3_ROUND, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI_INT) +BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fmadd_v4df_maskz_round, "__builtin_ia32_vfmaddpd256_maskz_round", IX86_BUILTIN_VFMADDPD256_MASKZ_ROUND, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI_INT) +BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fmadd_v16hf_mask_round, "__builtin_ia32_vfmaddph256_mask_round", IX86_BUILTIN_VFMADDPH256_MASK_ROUND, UNKNOWN, (int) V16HF_FTYPE_V16HF_V16HF_V16HF_UHI_INT) +BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fmadd_v16hf_mask3_round, "__builtin_ia32_vfmaddph256_mask3_round", IX86_BUILTIN_VFMADDPH512_MASK3_ROUND, UNKNOWN, (int) V16HF_FTYPE_V16HF_V16HF_V16HF_UHI_INT) +BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fmadd_v16hf_maskz_round, "__builtin_ia32_vfmaddph256_maskz_round", IX86_BUILTIN_VFMADDPH256_MASKZ_ROUND, UNKNOWN, (int) V16HF_FTYPE_V16HF_V16HF_V16HF_UHI_INT) +BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fmadd_v8sf_mask_round, "__builtin_ia32_vfmaddps256_mask_round", IX86_BUILTIN_VFMADDPS256_MASK_ROUND, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI_INT) +BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fmadd_v8sf_mask3_round, "__builtin_ia32_vfmaddps256_mask3_round", IX86_BUILTIN_VFMADDPS512_MASK3_ROUND, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI_INT) +BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fmadd_v8sf_maskz_round, "__builtin_ia32_vfmaddps256_maskz_round", IX86_BUILTIN_VFMADDPS256_MASKZ_ROUND, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI_INT) BDESC_END (ROUND_ARGS, MULTI_ARG) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 10640c6fef0..fe7520ac58a 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -5738,7 +5738,7 @@ (match_operand:VFH_AVX512VL 3 "register_operand" "0")) (match_dup 3) (match_operand: 4 "register_operand" "Yk")))] - "TARGET_AVX512F" + "TARGET_AVX512F && " "vfmadd231\t{%2, %1, %0%{%4%}|%0%{%4%}, %1, %2}" [(set_attr "type" "ssemuladd") (set_attr "prefix" "evex") diff --git a/gcc/testsuite/gcc.target/i386/avx-1.c b/gcc/testsuite/gcc.target/i386/avx-1.c index 2e5c2f2d786..9e6e609108e 100644 --- a/gcc/testsuite/gcc.target/i386/avx-1.c +++ b/gcc/testsuite/gcc.target/i386/avx-1.c @@ -909,6 +909,15 @@ #define __builtin_ia32_fixupimmpd256_maskz_round(A, B, C, I, E, F) __builtin_ia32_fixupimmpd256_maskz_round(A, B, C, 1, E, 8) #define __builtin_ia32_fixupimmps256_mask_round(A, B, C, I, E, F) __builtin_ia32_fixupimmps256_mask_round(A, B, C, 1, E, 8) #define __builtin_ia32_fixupimmps256_maskz_round(A, B, C, I, E, F) __builtin_ia32_fixupimmps256_maskz_round(A, B, C, 1, E, 8) +#define __builtin_ia32_vfmaddpd256_mask_round(A, B, C, D, E) __builtin_ia32_vfmaddpd256_mask_round(A, B, C, D, 8) +#define __builtin_ia32_vfmaddpd256_mask3_round(A, B, C, D, E) __builtin_ia32_vfmaddpd256_mask3_round(A, B, C, D, 8) +#define __builtin_ia32_vfmaddpd256_maskz_round(A, B, C, D, E) __builtin_ia32_vfmaddpd256_maskz_round(A, B, C, D, 8) +#define __builtin_ia32_vfmaddph256_mask_round(A, B, C, D, E) __builtin_ia32_vfmaddph256_mask_round(A, B, C, D, 8) +#define __builtin_ia32_vfmaddph256_mask3_round(A, B, C, D, E) __builtin_ia32_vfmaddph256_mask3_round(A, B, C, D, 8) +#define __builtin_ia32_vfmaddph256_maskz_round(A, B, C, D, E) __builtin_ia32_vfmaddph256_maskz_round(A, B, C, D, 8) +#define __builtin_ia32_vfmaddps256_mask_round(A, B, C, D, E) __builtin_ia32_vfmaddps256_mask_round(A, B, C, D, 8) +#define __builtin_ia32_vfmaddps256_mask3_round(A, B, C, D, E) __builtin_ia32_vfmaddps256_mask3_round(A, B, C, D, 8) +#define __builtin_ia32_vfmaddps256_maskz_round(A, B, C, D, E) __builtin_ia32_vfmaddps256_maskz_round(A, B, C, D, 8) #include #include diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-rounding-3.c b/gcc/testsuite/gcc.target/i386/avx10_2-rounding-3.c index 16dcb274909..e5a1831147c 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_2-rounding-3.c +++ b/gcc/testsuite/gcc.target/i386/avx10_2-rounding-3.c @@ -27,6 +27,18 @@ /* { dg-final { scan-assembler-times "vfixupimmps\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vfixupimmps\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vfixupimmps\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfmadd...pd\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfmadd...pd\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfmadd231pd\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfmadd...pd\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfmadd...ph\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfmadd...ph\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfmadd231ph\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfmadd...ph\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfmadd...ps\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfmadd...ps\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfmadd231ps\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfmadd...ps\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ #include @@ -105,3 +117,22 @@ avx10_2_test_6 (void) x = _mm256_mask_fixupimm_round_ps (x, m8, x, xi, 3, _MM_FROUND_NO_EXC); x = _mm256_maskz_fixupimm_round_ps (m8, x, x, xi, 3, _MM_FROUND_NO_EXC); } + +void extern +avx10_2_test_7 (void) +{ + xd = _mm256_fmadd_round_pd (xd, xd, xd, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC); + xd = _mm256_mask_fmadd_round_pd (xd, m8, xd, xd, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC); + xd = _mm256_mask3_fmadd_round_pd (xd, xd, xd, m8, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC); + xd = _mm256_maskz_fmadd_round_pd (m8, xd, xd, xd, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC); + + xh = _mm256_fmadd_round_ph (xh, xh, xh, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC); + xh = _mm256_mask_fmadd_round_ph (xh, m16, xh, xh, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC); + xh = _mm256_mask3_fmadd_round_ph (xh, xh, xh, m16, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC); + xh = _mm256_maskz_fmadd_round_ph (m16, xh, xh, xh, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC); + + x = _mm256_fmadd_round_ps (x, x, x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC); + x = _mm256_mask_fmadd_round_ps (x, m8, x, x, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC); + x = _mm256_mask3_fmadd_round_ps (x, x, x, m8, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC); + x = _mm256_maskz_fmadd_round_ps (m8, x, x, x, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC); +} diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c index b84791aeaae..d8e1ee6a99b 100644 --- a/gcc/testsuite/gcc.target/i386/sse-13.c +++ b/gcc/testsuite/gcc.target/i386/sse-13.c @@ -916,5 +916,14 @@ #define __builtin_ia32_fixupimmpd256_maskz_round(A, B, C, D, E, F) __builtin_ia32_fixupimmpd256_maskz_round(A, B, C, 1, E, 8) #define __builtin_ia32_fixupimmps256_mask_round(A, B, C, D, E, F) __builtin_ia32_fixupimmps256_mask_round(A, B, C, 1, E, 8) #define __builtin_ia32_fixupimmps256_maskz_round(A, B, C, D, E, F) __builtin_ia32_fixupimmps256_maskz_round(A, B, C, 1, E, 8) +#define __builtin_ia32_vfmaddpd256_mask_round(A, B, C, D, E) __builtin_ia32_vfmaddpd256_mask_round(A, B, C, D, 8) +#define __builtin_ia32_vfmaddpd256_mask3_round(A, B, C, D, E) __builtin_ia32_vfmaddpd256_mask3_round(A, B, C, D, 8) +#define __builtin_ia32_vfmaddpd256_maskz_round(A, B, C, D, E) __builtin_ia32_vfmaddpd256_maskz_round(A, B, C, D, 8) +#define __builtin_ia32_vfmaddph256_mask_round(A, B, C, D, E) __builtin_ia32_vfmaddph256_mask_round(A, B, C, D, 8) +#define __builtin_ia32_vfmaddph256_mask3_round(A, B, C, D, E) __builtin_ia32_vfmaddph256_mask3_round(A, B, C, D, 8) +#define __builtin_ia32_vfmaddph256_maskz_round(A, B, C, D, E) __builtin_ia32_vfmaddph256_maskz_round(A, B, C, D, 8) +#define __builtin_ia32_vfmaddps256_mask_round(A, B, C, D, E) __builtin_ia32_vfmaddps256_mask_round(A, B, C, D, 8) +#define __builtin_ia32_vfmaddps256_mask3_round(A, B, C, D, E) __builtin_ia32_vfmaddps256_mask3_round(A, B, C, D, 8) +#define __builtin_ia32_vfmaddps256_maskz_round(A, B, C, D, E) __builtin_ia32_vfmaddps256_maskz_round(A, B, C, D, 8) #include diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc/testsuite/gcc.target/i386/sse-14.c index c9fb7ec8345..0cf49a59a52 100644 --- a/gcc/testsuite/gcc.target/i386/sse-14.c +++ b/gcc/testsuite/gcc.target/i386/sse-14.c @@ -1178,6 +1178,9 @@ test_3 (_mm256_maskz_div_round_ph, __m256h, __mmask8, __m256h, __m256h, 9) test_3 (_mm256_maskz_div_round_ps, __m256, __mmask8, __m256, __m256, 9) test_3 (_mm256_fcmadd_round_pch, __m256h, __m256h, __m256h, __m256h, 8) test_3 (_mm256_maskz_fcmul_round_pch, __m256h, __mmask8, __m256h, __m256h, 8) +test_3 (_mm256_fmadd_round_pd, __m256d, __m256d, __m256d, __m256d, 9) +test_3 (_mm256_fmadd_round_ph, __m256h, __m256h, __m256h, __m256h, 9) +test_3 (_mm256_fmadd_round_ps, __m256, __m256, __m256, __m256, 9) test_3x (_mm256_mask_cmp_round_pd_mask, __mmask8, __mmask8, __m256d, __m256d, 1, 8) test_3x (_mm256_mask_cmp_round_ph_mask, __mmask16, __mmask16, __m256h, __m256h, 1, 8) test_3x (_mm256_mask_cmp_round_ps_mask, __mmask8, __mmask8, __m256, __m256, 1, 8) @@ -1193,6 +1196,15 @@ test_4 (_mm256_mask_fcmadd_round_pch, __m256h, __m256h, __mmask8, __m256h, __m25 test_4 (_mm256_mask3_fcmadd_round_pch, __m256h, __m256h, __m256h, __m256h, __mmask8, 9) test_4 (_mm256_maskz_fcmadd_round_pch, __m256h, __mmask8, __m256h, __m256h, __m256h, 9) test_4 (_mm256_mask_fcmul_round_pch, __m256h, __m256h, __mmask8, __m256h, __m256h, 8) +test_4 (_mm256_mask_fmadd_round_pd, __m256d, __m256d, __mmask8, __m256d, __m256d, 9) +test_4 (_mm256_mask3_fmadd_round_pd, __m256d, __m256d, __m256d, __m256d, __mmask8, 9) +test_4 (_mm256_maskz_fmadd_round_pd, __m256d, __mmask8, __m256d, __m256d, __m256d, 9) +test_4 (_mm256_mask_fmadd_round_ph, __m256h, __m256h, __mmask16, __m256h, __m256h, 9) +test_4 (_mm256_mask3_fmadd_round_ph, __m256h, __m256h, __m256h, __m256h, __mmask16, 9) +test_4 (_mm256_maskz_fmadd_round_ph, __m256h,__mmask16, __m256h, __m256h, __m256h, 9) +test_4 (_mm256_mask_fmadd_round_ps, __m256, __m256, __mmask8, __m256, __m256, 9) +test_4 (_mm256_mask3_fmadd_round_ps, __m256, __m256, __m256, __m256, __mmask8, 9) +test_4 (_mm256_maskz_fmadd_round_ps, __m256,__mmask8, __m256, __m256, __m256, 9) test_4x (_mm256_maskz_fixupimm_round_pd, __m256d, __mmask8, __m256d, __m256d, __m256i, 3, 8) test_4x (_mm256_maskz_fixupimm_round_ps, __m256, __mmask8, __m256, __m256, __m256i, 3, 8) test_4x (_mm256_mask_fixupimm_round_pd, __m256d, __m256d, __mmask8, __m256d, __m256i, 3, 8) diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc/testsuite/gcc.target/i386/sse-22.c index f9086ef03c3..9685dd072eb 100644 --- a/gcc/testsuite/gcc.target/i386/sse-22.c +++ b/gcc/testsuite/gcc.target/i386/sse-22.c @@ -1221,6 +1221,9 @@ test_3 (_mm256_maskz_div_round_ph, __m256h, __mmask8, __m256h, __m256h, 9) test_3 (_mm256_maskz_div_round_ps, __m256, __mmask8, __m256, __m256, 9) test_3 (_mm256_fcmadd_round_pch, __m256h, __m256h, __m256h, __m256h, 8) test_3 (_mm256_maskz_fcmul_round_pch, __m256h, __mmask8, __m256h, __m256h, 8) +test_3 (_mm256_fmadd_round_pd, __m256d, __m256d, __m256d, __m256d, 9) +test_3 (_mm256_fmadd_round_ph, __m256h, __m256h, __m256h, __m256h, 9) +test_3 (_mm256_fmadd_round_ps, __m256, __m256, __m256, __m256, 9) test_3x (_mm256_mask_cmp_round_pd_mask, __mmask8, __mmask8, __m256d, __m256d, 1, 8) test_3x (_mm256_mask_cmp_round_ph_mask, __mmask16, __mmask16, __m256h, __m256h, 1, 8) test_3x (_mm256_mask_cmp_round_ps_mask, __mmask8, __mmask8, __m256, __m256, 1, 8) @@ -1236,6 +1239,15 @@ test_4 (_mm256_mask_fcmadd_round_pch, __m256h, __m256h, __mmask8, __m256h, __m25 test_4 (_mm256_mask3_fcmadd_round_pch, __m256h, __m256h, __m256h, __m256h, __mmask8, 9) test_4 (_mm256_maskz_fcmadd_round_pch, __m256h, __mmask8, __m256h, __m256h, __m256h, 9) test_4 (_mm256_mask_fcmul_round_pch, __m256h, __m256h, __mmask8, __m256h, __m256h, 8) +test_4 (_mm256_mask_fmadd_round_pd, __m256d, __m256d, __mmask8, __m256d, __m256d, 9) +test_4 (_mm256_mask3_fmadd_round_pd, __m256d, __m256d, __m256d, __m256d, __mmask8, 9) +test_4 (_mm256_maskz_fmadd_round_pd, __m256d,__mmask8, __m256d, __m256d, __m256d, 9) +test_4 (_mm256_mask_fmadd_round_ph, __m256h, __m256h, __mmask16, __m256h, __m256h, 9) +test_4 (_mm256_mask3_fmadd_round_ph, __m256h, __m256h, __m256h, __m256h, __mmask16, 9) +test_4 (_mm256_maskz_fmadd_round_ph, __m256h,__mmask16, __m256h, __m256h, __m256h, 9) +test_4 (_mm256_mask_fmadd_round_ps, __m256, __m256, __mmask8, __m256, __m256, 9) +test_4 (_mm256_mask3_fmadd_round_ps, __m256, __m256, __m256, __m256, __mmask8, 9) +test_4 (_mm256_maskz_fmadd_round_ps, __m256,__mmask8, __m256, __m256, __m256, 9) test_4x (_mm256_maskz_fixupimm_round_pd, __m256d, __mmask8, __m256d, __m256d, __m256i, 3, 8) test_4x (_mm256_maskz_fixupimm_round_ps, __m256, __mmask8, __m256, __m256, __m256i, 3, 8) test_4x (_mm256_mask_fixupimm_round_pd, __m256d, __m256d, __mmask8, __m256d, __m256i, 3, 8) diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c index 9c42d969b62..4f54afabeb5 100644 --- a/gcc/testsuite/gcc.target/i386/sse-23.c +++ b/gcc/testsuite/gcc.target/i386/sse-23.c @@ -891,6 +891,15 @@ #define __builtin_ia32_fixupimmpd256_maskz_round(A, B, C, D, E, F) __builtin_ia32_fixupimmpd256_maskz_round(A, B, C, 1, E, 8) #define __builtin_ia32_fixupimmps256_mask_round(A, B, C, D, E, F) __builtin_ia32_fixupimmps256_mask_round(A, B, C, 1, E, 8) #define __builtin_ia32_fixupimmps256_maskz_round(A, B, C, D, E, F) __builtin_ia32_fixupimmps256_maskz_round(A, B, C, 1, E, 8) +#define __builtin_ia32_vfmaddpd256_mask_round(A, B, C, D, E) __builtin_ia32_vfmaddpd256_mask_round(A, B, C, D, 8) +#define __builtin_ia32_vfmaddpd256_mask3_round(A, B, C, D, E) __builtin_ia32_vfmaddpd256_mask3_round(A, B, C, D, 8) +#define __builtin_ia32_vfmaddpd256_maskz_round(A, B, C, D, E) __builtin_ia32_vfmaddpd256_maskz_round(A, B, C, D, 8) +#define __builtin_ia32_vfmaddph256_mask_round(A, B, C, D, E) __builtin_ia32_vfmaddph256_mask_round(A, B, C, D, 8) +#define __builtin_ia32_vfmaddph256_mask3_round(A, B, C, D, E) __builtin_ia32_vfmaddph256_mask3_round(A, B, C, D, 8) +#define __builtin_ia32_vfmaddph256_maskz_round(A, B, C, D, E) __builtin_ia32_vfmaddph256_maskz_round(A, B, C, D, 8) +#define __builtin_ia32_vfmaddps256_mask_round(A, B, C, D, E) __builtin_ia32_vfmaddps256_mask_round(A, B, C, D, 8) +#define __builtin_ia32_vfmaddps256_mask3_round(A, B, C, D, E) __builtin_ia32_vfmaddps256_mask3_round(A, B, C, D, 8) +#define __builtin_ia32_vfmaddps256_maskz_round(A, B, C, D, E) __builtin_ia32_vfmaddps256_maskz_round(A, B, C, D, 8) #pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,sha,xsavec,xsaves,clflushopt,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,vpclmulqdq,pconfig,wbnoinvd,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2-512")