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Tue, 13 Aug 2024 12:41:52 +0000 From: Victor Do Nascimento To: CC: , , , , , , "Victor Do Nascimento" Subject: [PATCH V2 01/10] optabs: Make all `*dot_prod_optab's modeled as conversions Date: Tue, 13 Aug 2024 13:41:41 +0100 Message-ID: <20240813124150.1168825-2-victor.donascimento@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240813124150.1168825-1-victor.donascimento@arm.com> References: <20240813124150.1168825-1-victor.donascimento@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM4PEPF00027A67:EE_|PAVPR08MB9084:EE_|AM4PEPF00027A66:EE_|AS2PR08MB9546:EE_ X-MS-Office365-Filtering-Correlation-Id: 1b1d5b88-806e-4ee4-9553-08dcbb9556db x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info-Original: D8Fu0zIvU5RksLC8WlcekRbRfleQO3DHniJAW1yH7tYHgXIc/5d5lj+4SJ1MvLhM48YG4Uu6g29tkLy0vDmNVOYLaq0fAoYC0x0joch3JFXYnC/a3fxyponVxq/vAPLgmR/Rotrkz79HfJnHy4VGDr14dC7e9RuD0jPV4lraYamZo+TxcJM4TcCEYmmddn4qSMXUbplK2NdeOKhFWSWCDultbWNyk6YRiVh1KjZSVTu/EBv7fqvYIOWAvcaWszL4QzTWMCwmDiBpPjm0e225Qi/vXQOapWlNj5fm6ds/AKEpavN/GqJdz78dJ2eKjRn1RVZkKWBDMvCkSFJcn9eG+LivU8fjzObYIJrr4jCKiI3xGglWLWWU0V/sV9Iu7CIwKEEiorlUIa1njw8ZZ+Zvinrz7+s/Zl3h5O580kyweA5ptVtgzGuvIvW7ZphpTwzvCbGAM5D6oD1sZO6k/K5XvdrXqpSfJvDuMPKAvmhpZzdS6a7j0cX1s6drflV4U4+Y3o+zGvMvYxBExS2cVnczTZOjS/hOCrDdEHNx0MRDuypnYzAzMlYlnBWSjfpi+/BwnWM0p0ba9+xZXrfkTfBgeUsikBB7IvDxRF+6sCPupUZM/cMRzTaUos/zMKNQKJzMhy2imH+H8zngkZuRKhwfTPbaHjEBQMIXYwt4p95rAyyZgMBVBYepM+yDSqNnWpyGsmLqEu6KyXGEmvLnIOAOLELzFlCVxXfvhHzljL1D+fTnSOcFDT9Iw+suJdMLpdRNHG61rlDrMCqDJgCK8he/V+EZ7SdMytXisLO6nqfqg1FhUlGS1B1he3zD5umEdGAKhWFfz7T4apdKLYOFEtVKh7mFB4OHh3sDdRGrGyJvwFD0vFPnERQgAQJUvPbCAgPq3pp+B0zAROKjdxeIEK5TC0mRKPxddXdDMWI4+BoG4DTUD0p3O7hopYlvYKwZfvb0PHrSuNM9v3RNtsykXzsAAAPCb254wRsOiCfIpfg8d6u2hbyGO2Xr17flF2Kn6hJ+EDpYBtFHYsLZbfPf8O2bp9QtaB2tpMbIAh/Etf+5dcW5iTJFZgVk+moprEJImIX9oInDFgENhpIFGxPDGqMMemZ6WBVcjnwopAv3MHE1FtBTovgsh0Ce1lY0V6OQidH7MMTkxpbZjJG/qmfT4hdzTpnTLKf+lccKn5nKUAy+10i79ev7TZMWuZMPxAy6YtRbM9qN+51Sc2tDB16TvsBBH8qHPhLET/4Hivufe32qSkgCcELQOfTyo+Jbc+QhExBZNvILX/HwkxOQ9vnnEkUNNeBZUYD+9dBQ9v2Jhr7MsiAWF2/zoJhg+mExkfhkIZJ9VKJV0VBXLkZa+1zlFnJTMlPUxCEJEY+3PXB/Er8JHchr/IWDRT53plRlRsej+aoPdD4g9qA0/CX9OXIRE+ZAKABjv1K1bwJnkyfe/yGvbQ9+wTCGcLj/YNAJDZIchmKa X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; 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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230040)(1800799024)(82310400026)(35042699022)(36860700013)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Aug 2024 12:42:05.9801 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1b1d5b88-806e-4ee4-9553-08dcbb9556db X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM4PEPF00027A66.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS2PR08MB9546 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FORGED_SPF_HELO, GIT_PATCH_0, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Given the specification in the GCC internals manual defines the {u|s}dot_prod standard name as taking "two signed elements of the same mode, adding them to a third operand of wider mode", there is currently ambiguity in the relationship between the mode of the first two arguments and that of the third. This vagueness means that, in theory, different modes may be supportable in the third argument. This flexibility would allow for a given backend to add to the accumulator a different number of vectorized products, e.g. A backend may provide instructions for both: accum += a[0] * b[0] + a[1] * b[1] + a[2] * b[2] + a[3] * b[3] and accum += a[0] * b[0] + a[1] * b[1], as is now seen in the SVE2.1 extension to AArch64. In spite of the aforementioned flexibility, modeling the dot-product operation as a direct optab means that we have no way to encode both input and the accumulator data modes into the backend pattern name, which prevents us from harnessing this flexibility. We therefore make all dot_prod optabs conversions, allowing, for example, for the encoding of both 2-way and 4-way dot product backend patterns. gcc/ChangeLog: * optabs.def (sdot_prod_optab): Convert from OPTAB_D to OPTAB_CD. (udot_prod_optab): Likewise. (usdot_prod_optab): Likewise. * doc/md.texi (Standard Names): update entries for u,s and us dot_prod names. --- gcc/doc/md.texi | 46 +++++++++++++++++++++------------------------- gcc/optabs.def | 6 +++--- 2 files changed, 24 insertions(+), 28 deletions(-) diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 5dc0d55edd6..aa1181a3320 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -5760,15 +5760,14 @@ for (i = 0; i < LEN + BIAS; i++) operand0 += operand2[i]; @end smallexample -@cindex @code{sdot_prod@var{m}} instruction pattern -@item @samp{sdot_prod@var{m}} - -Compute the sum of the products of two signed elements. -Operand 1 and operand 2 are of the same mode. Their -product, which is of a wider mode, is computed and added to operand 3. -Operand 3 is of a mode equal or wider than the mode of the product. The -result is placed in operand 0, which is of the same mode as operand 3. -@var{m} is the mode of operand 1 and operand 2. +@cindex @code{sdot_prod@var{m}@var{n}} instruction pattern +@item @samp{sdot_prod@var{m}@var{n}} + +Multiply operand 1 by operand 2 without loss of precision, given that +both operands contain signed elements. Add each product to the overlapping +element of operand 3 and store the result in operand 0. Operands 0 and 3 +have mode @var{m} and operands 1 and 2 have mode @var{n}, with @var{n} +having narrower elements than @var{m}. Semantically the expressions perform the multiplication in the following signs @@ -5778,15 +5777,14 @@ sdot == @dots{} @end smallexample -@cindex @code{udot_prod@var{m}} instruction pattern -@item @samp{udot_prod@var{m}} +@cindex @code{udot_prod@var{m}@var{n}} instruction pattern +@item @samp{udot_prod@var{m}@var{n}} -Compute the sum of the products of two unsigned elements. -Operand 1 and operand 2 are of the same mode. Their -product, which is of a wider mode, is computed and added to operand 3. -Operand 3 is of a mode equal or wider than the mode of the product. The -result is placed in operand 0, which is of the same mode as operand 3. -@var{m} is the mode of operand 1 and operand 2. +Multiply operand 1 by operand 2 without loss of precision, given that +both operands contain unsigned elements. Add each product to the overlapping +element of operand 3 and store the result in operand 0. Operands 0 and 3 +have mode @var{m} and operands 1 and 2 have mode @var{n}, with @var{n} +having narrower elements than @var{m}. Semantically the expressions perform the multiplication in the following signs @@ -5796,14 +5794,12 @@ udot == @dots{} @end smallexample -@cindex @code{usdot_prod@var{m}} instruction pattern -@item @samp{usdot_prod@var{m}} -Compute the sum of the products of elements of different signs. -Operand 1 must be unsigned and operand 2 signed. Their -product, which is of a wider mode, is computed and added to operand 3. -Operand 3 is of a mode equal or wider than the mode of the product. The -result is placed in operand 0, which is of the same mode as operand 3. -@var{m} is the mode of operand 1 and operand 2. +@cindex @code{usdot_prod@var{m}@var{n}} instruction pattern +@item @samp{usdot_prod@var{m}@var{n}} +Multiply operand 1 by operand 2. Add each product to the overlapping +element of operand 3 and store the result in operand 0. Operands 0 and 3 +have mode @var{m} and operands 1 and 2 have mode @var{n}, with @var{n} +having narrower elements than @var{m}. Semantically the expressions perform the multiplication in the following signs diff --git a/gcc/optabs.def b/gcc/optabs.def index 58a939442bd..ba860144d8b 100644 --- a/gcc/optabs.def +++ b/gcc/optabs.def @@ -110,6 +110,9 @@ OPTAB_CD(mask_scatter_store_optab, "mask_scatter_store$a$b") OPTAB_CD(mask_len_scatter_store_optab, "mask_len_scatter_store$a$b") OPTAB_CD(vec_extract_optab, "vec_extract$a$b") OPTAB_CD(vec_init_optab, "vec_init$a$b") +OPTAB_CD (sdot_prod_optab, "sdot_prod$I$a$b") +OPTAB_CD (udot_prod_optab, "udot_prod$I$a$b") +OPTAB_CD (usdot_prod_optab, "usdot_prod$I$a$b") OPTAB_CD (while_ult_optab, "while_ult$a$b") @@ -413,10 +416,7 @@ OPTAB_D (savg_floor_optab, "avg$a3_floor") OPTAB_D (uavg_floor_optab, "uavg$a3_floor") OPTAB_D (savg_ceil_optab, "avg$a3_ceil") OPTAB_D (uavg_ceil_optab, "uavg$a3_ceil") -OPTAB_D (sdot_prod_optab, "sdot_prod$I$a") OPTAB_D (ssum_widen_optab, "widen_ssum$I$a3") -OPTAB_D (udot_prod_optab, "udot_prod$I$a") -OPTAB_D (usdot_prod_optab, "usdot_prod$I$a") OPTAB_D (usum_widen_optab, "widen_usum$I$a3") OPTAB_D (usad_optab, "usad$I$a") OPTAB_D (ssad_optab, "ssad$I$a")