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X-CSE-ConnectionGUID: UtygkQFvSt+1sfVZn10f2Q== X-CSE-MsgGUID: Yst6zxeDQ1iy3a9CEJL19A== X-IronPort-AV: E=McAfee;i="6700,10204,11160"; a="21315929" X-IronPort-AV: E=Sophos;i="6.09,279,1716274800"; d="scan'208";a="21315929" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Aug 2024 05:36:50 -0700 X-CSE-ConnectionGUID: i5vRVXIURFGrmX2gMxuvMg== X-CSE-MsgGUID: V6lQceAfTuKYjQmKs2reqw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,279,1716274800"; d="scan'208";a="57707635" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orviesa010.jf.intel.com with ESMTP; 10 Aug 2024 05:36:49 -0700 Received: from panli.sh.intel.com (panli.sh.intel.com [10.239.154.73]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 3812A10056AC; Sat, 10 Aug 2024 20:36:48 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v1] RISC-V: Bugfix incorrect operand for vwsll auto-vect Date: Sat, 10 Aug 2024 20:36:36 +0800 Message-ID: <20240810123636.3620592-1-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li This patch would like to fix one ICE when rv64gcv_zvbb for vwsll. Consider below example. void vwsll_vv_test (short *restrict dst, char *restrict a, int *restrict b, int n) { for (int i = 0; i < n; i++) dst[i] = a[i] << b[i]; } It will hit the vwsll pattern with following operands. operand 0 -> (reg:RVVMF2HI 146 [ vect__7.13 ]) operand 1 -> (reg:RVVMF4QI 165 [ vect_cst__33 ]) operand 2 -> (reg:RVVM1SI 171 [ vect_cst__36 ]) According to the ISA, operand 2 should be the same as operand 1. Aka operand 2 should have RVVMF4QI mode as above. Thus, add quad truncation for operand 2 before emit vwsll. The below test suites are passed for this patch. * The rv64gcv fully regression test. PR target/116280 gcc/ChangeLog: * config/riscv/autovec-opt.md: Add quad truncation to align the mode requirement for vwsll. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr116280-1.c: New test. * gcc.target/riscv/rvv/base/pr116280-2.c: New test. Signed-off-by: Pan Li --- gcc/config/riscv/autovec-opt.md | 4 ++++ .../gcc.target/riscv/rvv/base/pr116280-1.c | 14 ++++++++++++++ .../gcc.target/riscv/rvv/base/pr116280-2.c | 10 ++++++++++ 3 files changed, 28 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-2.c diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index d7a3cfd4602..4b33a145c17 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -1546,6 +1546,10 @@ (define_insn_and_split "*vwsll_zext1_trunc_" "&& 1" [(const_int 0)] { + rtx truncated = gen_reg_rtx (mode); + emit_insn (gen_trunc2 (truncated, operands[2])); + operands[2] = truncated; + insn_code icode = code_for_pred_vwsll (mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands); DONE; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-1.c new file mode 100644 index 00000000000..8b8547e2c34 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-1.c @@ -0,0 +1,14 @@ +/* Test there is no ICE when compile. */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvbb -mabi=lp64d -O3" } */ + +short a; +char b; + +void +test (int e[][1][1], char f[][1][1][1][1]) { + for (int g; b;) + for (;;) + for (int h; h < 4073709551572ULL; h += 18446744073709551612U) + a = f[2][2][1][4073709551612][1] << e[1][1][g]; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-2.c new file mode 100644 index 00000000000..02f2de66eff --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-2.c @@ -0,0 +1,10 @@ +/* Test there is no ICE when compile. */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvbb -mabi=lp64d -O3" } */ + +void +test (short *restrict dst, char *restrict a, int *restrict b, int n) +{ + for (int i = 0; i < n; i++) + dst[i] = a[i] << b[i]; +}