From patchwork Thu Aug 8 06:47:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lulu Cheng X-Patchwork-Id: 1970384 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Wfd1H0lzcz1yfC for ; Thu, 8 Aug 2024 16:48:51 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 472973858432 for ; Thu, 8 Aug 2024 06:48:48 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 45B1D385842C for ; Thu, 8 Aug 2024 06:48:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 45B1D385842C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 45B1D385842C Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1723099705; cv=none; b=MwWY8cgxUr6rZ8jfIYWzvsYCea6PWGCXE5vD4o78ft4L7AR4dziGVd3lUEnq+vaFX41KaOr/aJAupZV6eVSBwTAqZlV0Ml+DrBQxEA1fygiljm+fNkGF+/knkXw5UTJKbxsCpkzjWfMlnCk2J39iS8t4ZErJQ4PxbIQpsSDF534= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1723099705; c=relaxed/simple; bh=viXkcf83FCa5OQHMMCc6TXb7Vn+6B3b5/j2gPe5+Hlw=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=kNDj1Rk4F+IQ+g59KbhnYjjCzNxxg4sR0mJDLlel0w9CHqIooK8I1KNAHyc9DCd/tct5jV+TUnYzbBlzBuTvJjDp1KA5Sh/X/v6TzBYQERkZZ8iV5QxhHbHYvA57PwUfD4cUqsnRdbbRRCmXhn/CDaEo7/YgnDIMipQ246388Jo= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from loongson.cn (unknown [10.20.4.107]) by gateway (Coremail) with SMTP id _____8Dxi+oyarRmv3wLAA--.34772S3; Thu, 08 Aug 2024 14:48:18 +0800 (CST) Received: from loongson-pc.loongson.cn (unknown [10.20.4.107]) by front1 (Coremail) with SMTP id qMiowMCxwuEgarRmv1EJAA--.46725S3; Thu, 08 Aug 2024 14:48:13 +0800 (CST) From: Lulu Cheng To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, chenglulu@loongson.cn Subject: [PATCH v1 2/2] LoongArch: Provide ashr lshr and ashl RTL pattern for vectors. Date: Thu, 8 Aug 2024 14:47:49 +0800 Message-Id: <20240808064747.9012-2-chenglulu@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20240808064747.9012-1-chenglulu@loongson.cn> References: <20240808064747.9012-1-chenglulu@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: qMiowMCxwuEgarRmv1EJAA--.46725S3 X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj93XoW3GFyUCry5JFWxJryUGFyDurX_yoWxtFy8pF ZxZ347GF4kt3W3Za4xJFyUJF4FvF48Kw42vryDGas5ArZ7JF9xXrZYqr1ayFyrAr15GryU uFn8WrWIgF4DGwcCm3ZEXasCq-sJn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkFb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AK xVW8Jr0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx 1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1Y6r17McIj6I8E87Iv 67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2 Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s02 6x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF0x vE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE 42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6x kF7I0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x07UNvtZUUUUU= X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org We support vashr vlshr and vashl. However, in r15-1638 support optimize x < 0 ? -1 : 0 into (signed) x >> 31 and x < 0 ? 1 : 0 into (unsigned) x >> 31. To support this optimization, vector ashr lshr and ashl need to be implemented. gcc/ChangeLog: * config/loongarch/loongarch.md (insn): Added rotatert rotr pairs. * config/loongarch/simd.md (rotr3): Remove to ... (3): This. gcc/testsuite/ChangeLog: * g++.target/loongarch/vect-ashr-lshr.C: New test. --- gcc/config/loongarch/loongarch.md | 1 + gcc/config/loongarch/simd.md | 13 +- .../g++.target/loongarch/vect-ashr-lshr.C | 147 ++++++++++++++++++ 3 files changed, 155 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/g++.target/loongarch/vect-ashr-lshr.C diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index ee0310f2bd6..1f105cbf891 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -559,6 +559,7 @@ (define_code_attr optab [(ashift "ashl") (define_code_attr insn [(ashift "sll") (ashiftrt "sra") (lshiftrt "srl") + (rotatert "rotr") (ior "or") (xor "xor") (and "and") diff --git a/gcc/config/loongarch/simd.md b/gcc/config/loongarch/simd.md index 00ff2823a4e..45ea114220e 100644 --- a/gcc/config/loongarch/simd.md +++ b/gcc/config/loongarch/simd.md @@ -306,14 +306,15 @@ (define_expand "rotl3" operands[4] = gen_reg_rtx (mode); }); -;; vrotri.{b/h/w/d} +;; v{rotr/sll/sra/srl}i.{b/h/w/d} -(define_insn "rotr3" +(define_insn "3" [(set (match_operand:IVEC 0 "register_operand" "=f") - (rotatert:IVEC (match_operand:IVEC 1 "register_operand" "f") - (match_operand:SI 2 "const__operand")))] - "" - "vrotri.\t%0,%1,%2"; + (shift_w:IVEC + (match_operand:IVEC 1 "register_operand" "f") + (match_operand:SI 2 "const__operand")))] + "ISA_HAS_LSX" + "vi.\t%0,%1,%2" [(set_attr "type" "simd_int_arith") (set_attr "mode" "")]) diff --git a/gcc/testsuite/g++.target/loongarch/vect-ashr-lshr.C b/gcc/testsuite/g++.target/loongarch/vect-ashr-lshr.C new file mode 100644 index 00000000000..bcef985fae2 --- /dev/null +++ b/gcc/testsuite/g++.target/loongarch/vect-ashr-lshr.C @@ -0,0 +1,147 @@ +/* { dg-do compile } */ +/* { dg-options "-mlasx -O2" } */ +/* { dg-final { scan-assembler-times "vsrli.b" 2 } } */ +/* { dg-final { scan-assembler-times "vsrli.h" 2 } } */ +/* { dg-final { scan-assembler-times "vsrli.w" 2 } } */ +/* { dg-final { scan-assembler-times "vsrli.d" 2 } } */ +/* { dg-final { scan-assembler-times "vsrai.b" 2 } } */ +/* { dg-final { scan-assembler-times "vsrai.h" 2 } } */ +/* { dg-final { scan-assembler-times "vsrai.w" 2 } } */ +/* { dg-final { scan-assembler-times "vsrai.d" 2 } } */ + +typedef signed char v16qi __attribute__((vector_size(16))); +typedef signed char v32qi __attribute__((vector_size(32))); +typedef short v8hi __attribute__((vector_size(16))); +typedef short v16hi __attribute__((vector_size(32))); +typedef int v4si __attribute__((vector_size(16))); +typedef int v8si __attribute__((vector_size(32))); +typedef long long v2di __attribute__((vector_size(16))); +typedef long long v4di __attribute__((vector_size(32))); + +v16qi +foo (v16qi a) +{ + v16qi const1_op = __extension__(v16qi){1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}; + v16qi const0_op = __extension__(v16qi){0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; + return a < const0_op ? const1_op : const0_op; +} + +v32qi +foo2 (v32qi a) +{ + v32qi const1_op = __extension__(v32qi){1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}; + v32qi const0_op = __extension__(v32qi){0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; + return a < const0_op ? const1_op : const0_op; +} + +v8hi +foo3 (v8hi a) +{ + v8hi const1_op = __extension__(v8hi){1,1,1,1,1,1,1,1}; + v8hi const0_op = __extension__(v8hi){0,0,0,0,0,0,0,0}; + return a < const0_op ? const1_op : const0_op; +} + +v16hi +foo4 (v16hi a) +{ + v16hi const1_op = __extension__(v16hi){1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}; + v16hi const0_op = __extension__(v16hi){0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; + return a < const0_op ? const1_op : const0_op; +} + +v4si +foo5 (v4si a) +{ + v4si const1_op = __extension__(v4si){1,1,1,1}; + v4si const0_op = __extension__(v4si){0,0,0,0}; + return a < const0_op ? const1_op : const0_op; +} + +v8si +foo6 (v8si a) +{ + v8si const1_op = __extension__(v8si){1,1,1,1,1,1,1,1}; + v8si const0_op = __extension__(v8si){0,0,0,0,0,0,0,0}; + return a < const0_op ? const1_op : const0_op; +} + +v2di +foo7 (v2di a) +{ + v2di const1_op = __extension__(v2di){1,1}; + v2di const0_op = __extension__(v2di){0,0}; + return a < const0_op ? const1_op : const0_op; +} + +v4di +foo8 (v4di a) +{ + v4di const1_op = __extension__(v4di){1,1,1,1}; + v4di const0_op = __extension__(v4di){0,0,0,0}; + return a < const0_op ? const1_op : const0_op; +} + +v16qi +foo9 (v16qi a) +{ + v16qi const1_op = __extension__(v16qi){-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1}; + v16qi const0_op = __extension__(v16qi){0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; + return a < const0_op ? const1_op : const0_op; +} + +v32qi +foo10 (v32qi a) +{ + v32qi const1_op = __extension__(v32qi){-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1}; + v32qi const0_op = __extension__(v32qi){0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; + return a < const0_op ? const1_op : const0_op; +} + +v8hi +foo11 (v8hi a) +{ + v8hi const1_op = __extension__(v8hi){-1,-1,-1,-1,-1,-1,-1,-1}; + v8hi const0_op = __extension__(v8hi){0,0,0,0,0,0,0,0}; + return a < const0_op ? const1_op : const0_op; +} + +v16hi +foo12 (v16hi a) +{ + v16hi const1_op = __extension__(v16hi){-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1}; + v16hi const0_op = __extension__(v16hi){0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; + return a < const0_op ? const1_op : const0_op; +} + +v4si +foo13 (v4si a) +{ + v4si const1_op = __extension__(v4si){-1,-1,-1,-1}; + v4si const0_op = __extension__(v4si){0,0,0,0}; + return a < const0_op ? const1_op : const0_op; +} + +v8si +foo14 (v8si a) +{ + v8si const1_op = __extension__(v8si){-1,-1,-1,-1,-1,-1,-1,-1}; + v8si const0_op = __extension__(v8si){0,0,0,0,0,0,0,0}; + return a < const0_op ? const1_op : const0_op; +} + +v2di +foo15 (v2di a) +{ + v2di const1_op = __extension__(v2di){-1,-1}; + v2di const0_op = __extension__(v2di){0,0}; + return a < const0_op ? const1_op : const0_op; +} + +v4di +foo16 (v4di a) +{ + v4di const1_op = __extension__(v4di){-1,-1,-1,-1}; + v4di const0_op = __extension__(v4di){0,0,0,0}; + return a < const0_op ? const1_op : const0_op; +}