diff mbox series

aarch64/testsuite: Add testcases for recently fixed PRs

Message ID 20240807164716.736040-1-quic_apinski@quicinc.com
State New
Headers show
Series aarch64/testsuite: Add testcases for recently fixed PRs | expand

Commit Message

Andrew Pinski Aug. 7, 2024, 4:47 p.m. UTC 
The commit for PR 116258, added a x86_64 specific testcase,
I thought it would be a good idea to add an aarch64 testcase too.
And since it also fixed VLA vectors too so add a SVE testcase.

Pushed as obvious after a test for aarch64-linux-gnu.

	PR middle-end/116258
	PR middle-end/116259

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/pr116258.c: New test.
	* gcc.target/aarch64/sve/pr116259-1.c: New test.

Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
---
 gcc/testsuite/gcc.target/aarch64/pr116258.c     | 17 +++++++++++++++++
 .../gcc.target/aarch64/sve/pr116259-1.c         | 12 ++++++++++++
 2 files changed, 29 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/aarch64/pr116258.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pr116259-1.c
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/aarch64/pr116258.c b/gcc/testsuite/gcc.target/aarch64/pr116258.c
new file mode 100644
index 00000000000..e727ad4b72a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pr116258.c
@@ -0,0 +1,17 @@ 
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#pragma GCC target "+nosve"
+
+#define vect16 __attribute__((vector_size(16)))
+#define h(a) __builtin_assoc_barrier((a))
+
+ vect16 float  f( vect16 float  x, vect16 float vconstants0)
+{
+  vect16 float  t = (x * (vconstants0[0]));
+  return (x + h(t));
+}
+
+/* { dg-final { scan-assembler-times "\\\[0\\\]" 1 } } */
+/* { dg-final { scan-assembler-not "dup\t" } } */
+/* { dg-final { scan-assembler-not "ins\t" } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr116259-1.c b/gcc/testsuite/gcc.target/aarch64/sve/pr116259-1.c
new file mode 100644
index 00000000000..bb2eed4728c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pr116259-1.c
@@ -0,0 +1,12 @@ 
+/* { dg-do compile } */
+/* PR middle-end/116259 */
+
+#include <arm_sve.h>
+
+/* PAREN_EXPR lowering for VLA vectors was ICEing.
+   It should not be lowered in a similar way as moves
+   are not lowered.  */
+svfloat64_t f(svfloat64_t x)
+{
+  return __builtin_assoc_barrier(x);
+}