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Tue, 06 Aug 2024 23:09:32 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA04.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 476N9VDF002574 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 6 Aug 2024 23:09:31 GMT Received: from hu-apinski-lv.qualcomm.com (10.49.16.6) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 6 Aug 2024 16:09:30 -0700 From: Andrew Pinski To: CC: Andrew Pinski Subject: [PATCH] aarch64/testsuite: Fix if-compare_2.c for removing vcond{, u, eq} patterns [PR116041] Date: Tue, 6 Aug 2024 16:09:20 -0700 Message-ID: <20240806230920.349132-1-quic_apinski@quicinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: cykMfq-ArEKJJLcik_qzej5qFU7RHTRo X-Proofpoint-GUID: cykMfq-ArEKJJLcik_qzej5qFU7RHTRo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-06_18,2024-08-06_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 suspectscore=0 mlxscore=0 malwarescore=0 mlxlogscore=999 phishscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408060162 X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org For bar1 and bar2, we currently is expecting to use the bsl instruction but with slightly different register allocation inside the loop (which happens after the removal of the vcond{,u,eq} patterns), we get the bit instruction. The pattern that outputs bsl instruction will output bit and bif too depending register allocation. So let's check for bsl, bit or bif instructions instead of just bsl instruction. Tested on aarch64 both with an unmodified compiler and one which has the patch to disable these optabs. gcc/testsuite/ChangeLog: PR testsuite/116041 * gcc.target/aarch64/if-compare_2.c: Support bit and bif for both bar1 and bar2; add comment on why too. Signed-off-by: Andrew Pinski --- gcc/testsuite/gcc.target/aarch64/if-compare_2.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/gcc/testsuite/gcc.target/aarch64/if-compare_2.c b/gcc/testsuite/gcc.target/aarch64/if-compare_2.c index 14988abac45..f5a2b1956e3 100644 --- a/gcc/testsuite/gcc.target/aarch64/if-compare_2.c +++ b/gcc/testsuite/gcc.target/aarch64/if-compare_2.c @@ -8,6 +8,7 @@ typedef int v4si __attribute__ ((vector_size (16))); + /* **foo1: ** cmgt v0.4s, v1.4s, v0.4s @@ -29,11 +30,13 @@ v4si foo2 (v4si a, v4si b, v4si c, v4si d) { } +/* The bsl could be bit or bif depending on register + allocator inside the loop. */ /** **bar1: **... ** cmge v[0-9]+.4s, v[0-9]+.4s, v[0-9]+.4s -** bsl v[0-9]+.16b, v[0-9]+.16b, v[0-9]+.16b +** (bsl|bit|bif) v[0-9]+.16b, v[0-9]+.16b, v[0-9]+.16b ** and v[0-9]+.16b, v[0-9]+.16b, v[0-9]+.16b **... */ @@ -44,11 +47,13 @@ void bar1 (int * restrict a, int * restrict b, int * restrict c, res[i] = ((a[i] < b[i]) & c[i]) | ((a[i] >= b[i]) & d[i]); } +/* The bsl could be bit or bif depending on register + allocator inside the loop. */ /** **bar2: **... ** cmge v[0-9]+.4s, v[0-9]+.4s, v[0-9]+.4s -** bsl v[0-9]+.16b, v[0-9]+.16b, v[0-9]+.16b +** (bsl|bit|bif) v[0-9]+.16b, v[0-9]+.16b, v[0-9]+.16b **... */ void bar2 (int * restrict a, int * restrict b, int * restrict c,