| Message ID | 20240731062932.1819010-2-claudio.bantaloukas@arm.com |
|---|---|
| State | New |
| Headers | show |
| Series | aarch64: Add initial support for +fp8 arch extensions | expand |
Hi Claudio, > On 31 Jul 2024, at 08:29, Claudio Bantaloukas <claudio.bantaloukas@arm.com> wrote: > > External email: Use caution opening links or attachments > > > This introduces the relevant flags to enable access to the fpmr register and fp8 intrinsics, which will be added subsequently. > > gcc/ChangeLog: > > * config/aarch64/aarch64-option-extensions.def (fp8): New. > * config/aarch64/aarch64.h (TARGET_FP8): Likewise. > * doc/invoke.texi (AArch64 Options): Document new -march flags > and extensions. > > gcc/testsuite/ChangeLog: > > * gcc.target/aarch64/acle/fp8.c: New test. Thank you for the explanations and the respins. This is ok. Thanks, Kyrill > --- > .../aarch64/aarch64-option-extensions.def | 2 ++ > gcc/config/aarch64/aarch64.h | 3 +++ > gcc/doc/invoke.texi | 2 ++ > gcc/testsuite/gcc.target/aarch64/acle/fp8.c | 20 +++++++++++++++++++ > 4 files changed, 27 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/fp8.c > > diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def > index 42ec0eec31e..6998627f377 100644 > --- a/gcc/config/aarch64/aarch64-option-extensions.def > +++ b/gcc/config/aarch64/aarch64-option-extensions.def > @@ -232,6 +232,8 @@ AARCH64_OPT_EXTENSION("the", THE, (), (), (), "the") > > AARCH64_OPT_EXTENSION("gcs", GCS, (), (), (), "gcs") > > +AARCH64_OPT_EXTENSION("fp8", FP8, (SIMD), (), (), "fp8") > + > #undef AARCH64_OPT_FMV_EXTENSION > #undef AARCH64_OPT_EXTENSION > #undef AARCH64_FMV_FEATURE > diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h > index b7e330438d9..2e75c6b81e2 100644 > --- a/gcc/config/aarch64/aarch64.h > +++ b/gcc/config/aarch64/aarch64.h > @@ -463,6 +463,9 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED > && (aarch64_tune_params.extra_tuning_flags \ > & AARCH64_EXTRA_TUNE_AVOID_PRED_RMW)) > > +/* fp8 instructions are enabled through +fp8. */ > +#define TARGET_FP8 AARCH64_HAVE_ISA (FP8) > + > /* Standard register usage. */ > > /* 31 64-bit general purpose registers R0-R30: > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi > index 86f9b5d1fe5..ef2213b4e84 100644 > --- a/gcc/doc/invoke.texi > +++ b/gcc/doc/invoke.texi > @@ -21849,6 +21849,8 @@ Enable support for Armv9.4-a Guarded Control Stack extension. > Enable support for Armv8.9-a/9.4-a translation hardening extension. > @item rcpc3 > Enable the RCpc3 (Release Consistency) extension. > +@item fp8 > +Enable the fp8 (8-bit floating point) extension. > > @end table > > diff --git a/gcc/testsuite/gcc.target/aarch64/acle/fp8.c b/gcc/testsuite/gcc.target/aarch64/acle/fp8.c > new file mode 100644 > index 00000000000..459442be155 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/acle/fp8.c > @@ -0,0 +1,20 @@ > +/* Test the fp8 ACLE intrinsics family. */ > +/* { dg-do compile } */ > +/* { dg-options "-O1 -march=armv8-a" } */ > + > +#include <arm_acle.h> > + > +#ifdef __ARM_FEATURE_FP8 > +#error "__ARM_FEATURE_FP8 feature macro defined." > +#endif > + > +#pragma GCC push_options > +#pragma GCC target("arch=armv9.4-a+fp8") > + > +/* We do not define __ARM_FEATURE_FP8 until all > + relevant features have been added. */ > +#ifdef __ARM_FEATURE_FP8 > +#error "__ARM_FEATURE_FP8 feature macro defined." > +#endif > + > +#pragma GCC pop_options
diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def index 42ec0eec31e..6998627f377 100644 --- a/gcc/config/aarch64/aarch64-option-extensions.def +++ b/gcc/config/aarch64/aarch64-option-extensions.def @@ -232,6 +232,8 @@ AARCH64_OPT_EXTENSION("the", THE, (), (), (), "the") AARCH64_OPT_EXTENSION("gcs", GCS, (), (), (), "gcs") +AARCH64_OPT_EXTENSION("fp8", FP8, (SIMD), (), (), "fp8") + #undef AARCH64_OPT_FMV_EXTENSION #undef AARCH64_OPT_EXTENSION #undef AARCH64_FMV_FEATURE diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index b7e330438d9..2e75c6b81e2 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -463,6 +463,9 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED && (aarch64_tune_params.extra_tuning_flags \ & AARCH64_EXTRA_TUNE_AVOID_PRED_RMW)) +/* fp8 instructions are enabled through +fp8. */ +#define TARGET_FP8 AARCH64_HAVE_ISA (FP8) + /* Standard register usage. */ /* 31 64-bit general purpose registers R0-R30: diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 86f9b5d1fe5..ef2213b4e84 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -21849,6 +21849,8 @@ Enable support for Armv9.4-a Guarded Control Stack extension. Enable support for Armv8.9-a/9.4-a translation hardening extension. @item rcpc3 Enable the RCpc3 (Release Consistency) extension. +@item fp8 +Enable the fp8 (8-bit floating point) extension. @end table diff --git a/gcc/testsuite/gcc.target/aarch64/acle/fp8.c b/gcc/testsuite/gcc.target/aarch64/acle/fp8.c new file mode 100644 index 00000000000..459442be155 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/fp8.c @@ -0,0 +1,20 @@ +/* Test the fp8 ACLE intrinsics family. */ +/* { dg-do compile } */ +/* { dg-options "-O1 -march=armv8-a" } */ + +#include <arm_acle.h> + +#ifdef __ARM_FEATURE_FP8 +#error "__ARM_FEATURE_FP8 feature macro defined." +#endif + +#pragma GCC push_options +#pragma GCC target("arch=armv9.4-a+fp8") + +/* We do not define __ARM_FEATURE_FP8 until all + relevant features have been added. */ +#ifdef __ARM_FEATURE_FP8 +#error "__ARM_FEATURE_FP8 feature macro defined." +#endif + +#pragma GCC pop_options