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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230040)(34020700016)(82310400026)(376014)(36860700013)(1800799024)(35042699022); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jul 2024 16:33:09.0026 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 78a2a44e-d407-48d1-6021-08dcad90a25a X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AMS1EPF00000045.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR08MB7906 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FORGED_SPF_HELO, GIT_PATCH_0, KAM_SHORT, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org This introduces the relevant flags to enable access to the fpmr register and fp8 intrinsics, which will be added subsequently. gcc/ChangeLog: * config/aarch64/aarch64-option-extensions.def (fp8): New. * config/aarch64/aarch64.h (TARGET_FP8): Likewise. * doc/invoke.texi (AArch64 Options): Document new -march flags and extensions. gcc/testsuite/ChangeLog: * gcc.target/aarch64/acle/fp8.c: New test. --- .../aarch64/aarch64-option-extensions.def | 2 ++ gcc/config/aarch64/aarch64.h | 3 +++ gcc/doc/invoke.texi | 2 ++ gcc/testsuite/gcc.target/aarch64/acle/fp8.c | 20 +++++++++++++++++++ 4 files changed, 27 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/fp8.c diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def index 42ec0eec31e..6998627f377 100644 --- a/gcc/config/aarch64/aarch64-option-extensions.def +++ b/gcc/config/aarch64/aarch64-option-extensions.def @@ -232,6 +232,8 @@ AARCH64_OPT_EXTENSION("the", THE, (), (), (), "the") AARCH64_OPT_EXTENSION("gcs", GCS, (), (), (), "gcs") +AARCH64_OPT_EXTENSION("fp8", FP8, (SIMD), (), (), "fp8") + #undef AARCH64_OPT_FMV_EXTENSION #undef AARCH64_OPT_EXTENSION #undef AARCH64_FMV_FEATURE diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index b7e330438d9..2e75c6b81e2 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -463,6 +463,9 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED && (aarch64_tune_params.extra_tuning_flags \ & AARCH64_EXTRA_TUNE_AVOID_PRED_RMW)) +/* fp8 instructions are enabled through +fp8. */ +#define TARGET_FP8 AARCH64_HAVE_ISA (FP8) + /* Standard register usage. */ /* 31 64-bit general purpose registers R0-R30: diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 9fb0925ed29..7cbcd8ad1b4 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -21848,6 +21848,8 @@ Enable support for Armv9.4-a Guarded Control Stack extension. Enable support for Armv8.9-a/9.4-a translation hardening extension. @item rcpc3 Enable the RCpc3 (Release Consistency) extension. +@item fp8 +Enable the fp8 (8-bit floating point) extension. @end table diff --git a/gcc/testsuite/gcc.target/aarch64/acle/fp8.c b/gcc/testsuite/gcc.target/aarch64/acle/fp8.c new file mode 100644 index 00000000000..459442be155 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/fp8.c @@ -0,0 +1,20 @@ +/* Test the fp8 ACLE intrinsics family. */ +/* { dg-do compile } */ +/* { dg-options "-O1 -march=armv8-a" } */ + +#include + +#ifdef __ARM_FEATURE_FP8 +#error "__ARM_FEATURE_FP8 feature macro defined." +#endif + +#pragma GCC push_options +#pragma GCC target("arch=armv9.4-a+fp8") + +/* We do not define __ARM_FEATURE_FP8 until all + relevant features have been added. */ +#ifdef __ARM_FEATURE_FP8 +#error "__ARM_FEATURE_FP8 feature macro defined." +#endif + +#pragma GCC pop_options