diff mbox series

[v3,1/3] aarch64: Add march flags for +fp8 arch extensions

Message ID 20240726163254.1174686-2-claudio.bantaloukas@arm.com
State New
Headers show
Series aarch64: Add initial support for +fp8 arch extensions | expand

Commit Message

Claudio Bantaloukas July 26, 2024, 4:32 p.m. UTC 
This introduces the relevant flags to enable access to the fpmr register and fp8 intrinsics, which will be added subsequently.

gcc/ChangeLog:

	* config/aarch64/aarch64-option-extensions.def (fp8): New.
	* config/aarch64/aarch64.h (TARGET_FP8): Likewise.
	* doc/invoke.texi (AArch64 Options): Document new -march flags
	and extensions.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/acle/fp8.c: New test.
---
 .../aarch64/aarch64-option-extensions.def     |  2 ++
 gcc/config/aarch64/aarch64.h                  |  3 +++
 gcc/doc/invoke.texi                           |  2 ++
 gcc/testsuite/gcc.target/aarch64/acle/fp8.c   | 20 +++++++++++++++++++
 4 files changed, 27 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/fp8.c

Comments

Kyrylo Tkachov July 29, 2024, 7:30 a.m. UTC | #1 
Hi Claudio,

> On 26 Jul 2024, at 18:32, Claudio Bantaloukas <claudio.bantaloukas@arm.com> wrote:
> 
> External email: Use caution opening links or attachments
> 
> 
> This introduces the relevant flags to enable access to the fpmr register and fp8 intrinsics, which will be added subsequently.
> 
> gcc/ChangeLog:
> 
>        * config/aarch64/aarch64-option-extensions.def (fp8): New.
>        * config/aarch64/aarch64.h (TARGET_FP8): Likewise.
>        * doc/invoke.texi (AArch64 Options): Document new -march flags
>        and extensions.
> 
> gcc/testsuite/ChangeLog:
> 
>        * gcc.target/aarch64/acle/fp8.c: New test.

Thanks, this looks ok to me now.
One question about the command-line flag.
FP8 defines instructions for Advanced SIMD, SVE and SME.
Is the “+fp8” option in this patch intended to combine with the +sve and +sme options to indicate the presence of these ISA-specific subsets? That is, you’re not planning to introduce something like +sve-fp8, +sme-fp8?
Kyrill


> ---
> .../aarch64/aarch64-option-extensions.def     |  2 ++
> gcc/config/aarch64/aarch64.h                  |  3 +++
> gcc/doc/invoke.texi                           |  2 ++
> gcc/testsuite/gcc.target/aarch64/acle/fp8.c   | 20 +++++++++++++++++++
> 4 files changed, 27 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/fp8.c
> 
> diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def
> index 42ec0eec31e..6998627f377 100644
> --- a/gcc/config/aarch64/aarch64-option-extensions.def
> +++ b/gcc/config/aarch64/aarch64-option-extensions.def
> @@ -232,6 +232,8 @@ AARCH64_OPT_EXTENSION("the", THE, (), (), (), "the")
> 
> AARCH64_OPT_EXTENSION("gcs", GCS, (), (), (), "gcs")
> 
> +AARCH64_OPT_EXTENSION("fp8", FP8, (SIMD), (), (), "fp8")
> +
> #undef AARCH64_OPT_FMV_EXTENSION
> #undef AARCH64_OPT_EXTENSION
> #undef AARCH64_FMV_FEATURE
> diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
> index b7e330438d9..2e75c6b81e2 100644
> --- a/gcc/config/aarch64/aarch64.h
> +++ b/gcc/config/aarch64/aarch64.h
> @@ -463,6 +463,9 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED
> && (aarch64_tune_params.extra_tuning_flags \
>     & AARCH64_EXTRA_TUNE_AVOID_PRED_RMW))
> 
> +/* fp8 instructions are enabled through +fp8.  */
> +#define TARGET_FP8 AARCH64_HAVE_ISA (FP8)
> +
> /* Standard register usage.  */
> 
> /* 31 64-bit general purpose registers R0-R30:
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> index 9fb0925ed29..7cbcd8ad1b4 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -21848,6 +21848,8 @@ Enable support for Armv9.4-a Guarded Control Stack extension.
> Enable support for Armv8.9-a/9.4-a translation hardening extension.
> @item rcpc3
> Enable the RCpc3 (Release Consistency) extension.
> +@item fp8
> +Enable the fp8 (8-bit floating point) extension.
> 
> @end table
> 
> diff --git a/gcc/testsuite/gcc.target/aarch64/acle/fp8.c b/gcc/testsuite/gcc.target/aarch64/acle/fp8.c
> new file mode 100644
> index 00000000000..459442be155
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/acle/fp8.c
> @@ -0,0 +1,20 @@
> +/* Test the fp8 ACLE intrinsics family.  */
> +/* { dg-do compile } */
> +/* { dg-options "-O1 -march=armv8-a" } */
> +
> +#include <arm_acle.h>
> +
> +#ifdef __ARM_FEATURE_FP8
> +#error "__ARM_FEATURE_FP8 feature macro defined."
> +#endif
> +
> +#pragma GCC push_options
> +#pragma GCC target("arch=armv9.4-a+fp8")
> +
> +/* We do not define __ARM_FEATURE_FP8 until all
> +   relevant features have been added. */
> +#ifdef __ARM_FEATURE_FP8
> +#error "__ARM_FEATURE_FP8 feature macro defined."
> +#endif
> +
> +#pragma GCC pop_options
Claudio Bantaloukas July 30, 2024, 1:41 p.m. UTC | #2 
On 29/07/2024 08:30, Kyrylo Tkachov wrote:
> Hi Claudio,
> 
>> On 26 Jul 2024, at 18:32, Claudio Bantaloukas <claudio.bantaloukas@arm.com> wrote:
>>
>> External email: Use caution opening links or attachments
>>
>>
>> This introduces the relevant flags to enable access to the fpmr register and fp8 intrinsics, which will be added subsequently.
>>
>> gcc/ChangeLog:
>>
>>         * config/aarch64/aarch64-option-extensions.def (fp8): New.
>>         * config/aarch64/aarch64.h (TARGET_FP8): Likewise.
>>         * doc/invoke.texi (AArch64 Options): Document new -march flags
>>         and extensions.
>>
>> gcc/testsuite/ChangeLog:
>>
>>         * gcc.target/aarch64/acle/fp8.c: New test.
> 
> Thanks, this looks ok to me now.
> One question about the command-line flag.
> FP8 defines instructions for Advanced SIMD, SVE and SME.
> Is the “+fp8” option in this patch intended to combine with the +sve and +sme options to indicate the presence of these ISA-specific subsets? That is, you’re not planning to introduce something like +sve-fp8, +sme-fp8?
> Kyrill

Hi Kyrill, thanks!
The plan is to have more specific feature flags like +fp8fma 
+ssve-fp8fma and +sme-lutv. +fp8 will only be used for conversion and 
scaling operations and my undestanding is that it will not combine as 
you propose.

See also the relevant binutils features in 
https://sourceware.org/git/?p=binutils-gdb.git;a=blob;f=gas/config/tc-aarch64.c;h=e94a0cff406aaaf1800979a27991ccbb7e92e917;hb=HEAD#l10731

Cheers,
Claudio

> 
>> ---
>> .../aarch64/aarch64-option-extensions.def     |  2 ++
>> gcc/config/aarch64/aarch64.h                  |  3 +++
>> gcc/doc/invoke.texi                           |  2 ++
>> gcc/testsuite/gcc.target/aarch64/acle/fp8.c   | 20 +++++++++++++++++++
>> 4 files changed, 27 insertions(+)
>> create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/fp8.c
>>
>> diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def
>> index 42ec0eec31e..6998627f377 100644
>> --- a/gcc/config/aarch64/aarch64-option-extensions.def
>> +++ b/gcc/config/aarch64/aarch64-option-extensions.def
>> @@ -232,6 +232,8 @@ AARCH64_OPT_EXTENSION("the", THE, (), (), (), "the")
>>
>> AARCH64_OPT_EXTENSION("gcs", GCS, (), (), (), "gcs")
>>
>> +AARCH64_OPT_EXTENSION("fp8", FP8, (SIMD), (), (), "fp8")
>> +
>> #undef AARCH64_OPT_FMV_EXTENSION
>> #undef AARCH64_OPT_EXTENSION
>> #undef AARCH64_FMV_FEATURE
>> diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
>> index b7e330438d9..2e75c6b81e2 100644
>> --- a/gcc/config/aarch64/aarch64.h
>> +++ b/gcc/config/aarch64/aarch64.h
>> @@ -463,6 +463,9 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED
>> && (aarch64_tune_params.extra_tuning_flags \
>>      & AARCH64_EXTRA_TUNE_AVOID_PRED_RMW))
>>
>> +/* fp8 instructions are enabled through +fp8.  */
>> +#define TARGET_FP8 AARCH64_HAVE_ISA (FP8)
>> +
>> /* Standard register usage.  */
>>
>> /* 31 64-bit general purpose registers R0-R30:
>> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
>> index 9fb0925ed29..7cbcd8ad1b4 100644
>> --- a/gcc/doc/invoke.texi
>> +++ b/gcc/doc/invoke.texi
>> @@ -21848,6 +21848,8 @@ Enable support for Armv9.4-a Guarded Control Stack extension.
>> Enable support for Armv8.9-a/9.4-a translation hardening extension.
>> @item rcpc3
>> Enable the RCpc3 (Release Consistency) extension.
>> +@item fp8
>> +Enable the fp8 (8-bit floating point) extension.
>>
>> @end table
>>
>> diff --git a/gcc/testsuite/gcc.target/aarch64/acle/fp8.c b/gcc/testsuite/gcc.target/aarch64/acle/fp8.c
>> new file mode 100644
>> index 00000000000..459442be155
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/aarch64/acle/fp8.c
>> @@ -0,0 +1,20 @@
>> +/* Test the fp8 ACLE intrinsics family.  */
>> +/* { dg-do compile } */
>> +/* { dg-options "-O1 -march=armv8-a" } */
>> +
>> +#include <arm_acle.h>
>> +
>> +#ifdef __ARM_FEATURE_FP8
>> +#error "__ARM_FEATURE_FP8 feature macro defined."
>> +#endif
>> +
>> +#pragma GCC push_options
>> +#pragma GCC target("arch=armv9.4-a+fp8")
>> +
>> +/* We do not define __ARM_FEATURE_FP8 until all
>> +   relevant features have been added. */
>> +#ifdef __ARM_FEATURE_FP8
>> +#error "__ARM_FEATURE_FP8 feature macro defined."
>> +#endif
>> +
>> +#pragma GCC pop_options
>
diff mbox series

Patch

diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def
index 42ec0eec31e..6998627f377 100644
--- a/gcc/config/aarch64/aarch64-option-extensions.def
+++ b/gcc/config/aarch64/aarch64-option-extensions.def
@@ -232,6 +232,8 @@  AARCH64_OPT_EXTENSION("the", THE, (), (), (), "the")
 
 AARCH64_OPT_EXTENSION("gcs", GCS, (), (), (), "gcs")
 
+AARCH64_OPT_EXTENSION("fp8", FP8, (SIMD), (), (), "fp8")
+
 #undef AARCH64_OPT_FMV_EXTENSION
 #undef AARCH64_OPT_EXTENSION
 #undef AARCH64_FMV_FEATURE
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index b7e330438d9..2e75c6b81e2 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -463,6 +463,9 @@  constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED
 				 && (aarch64_tune_params.extra_tuning_flags \
 				     & AARCH64_EXTRA_TUNE_AVOID_PRED_RMW))
 
+/* fp8 instructions are enabled through +fp8.  */
+#define TARGET_FP8 AARCH64_HAVE_ISA (FP8)
+
 /* Standard register usage.  */
 
 /* 31 64-bit general purpose registers R0-R30:
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 9fb0925ed29..7cbcd8ad1b4 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -21848,6 +21848,8 @@  Enable support for Armv9.4-a Guarded Control Stack extension.
 Enable support for Armv8.9-a/9.4-a translation hardening extension.
 @item rcpc3
 Enable the RCpc3 (Release Consistency) extension.
+@item fp8
+Enable the fp8 (8-bit floating point) extension.
 
 @end table
 
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/fp8.c b/gcc/testsuite/gcc.target/aarch64/acle/fp8.c
new file mode 100644
index 00000000000..459442be155
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/fp8.c
@@ -0,0 +1,20 @@ 
+/* Test the fp8 ACLE intrinsics family.  */
+/* { dg-do compile } */
+/* { dg-options "-O1 -march=armv8-a" } */
+
+#include <arm_acle.h>
+
+#ifdef __ARM_FEATURE_FP8
+#error "__ARM_FEATURE_FP8 feature macro defined."
+#endif
+
+#pragma GCC push_options
+#pragma GCC target("arch=armv9.4-a+fp8")
+
+/* We do not define __ARM_FEATURE_FP8 until all
+   relevant features have been added. */
+#ifdef __ARM_FEATURE_FP8
+#error "__ARM_FEATURE_FP8 feature macro defined."
+#endif
+
+#pragma GCC pop_options