diff mbox series

Fix mismatch between constraint and predicate for ashl<mode>3_doubleword.

Message ID 20240726065659.3929919-1-hongtao.liu@intel.com
State New
Headers show
Series Fix mismatch between constraint and predicate for ashl<mode>3_doubleword. | expand

Commit Message

liuhongt July 26, 2024, 6:56 a.m. UTC 
(insn 98 94 387 2 (parallel [
            (set (reg:TI 337 [ _32 ])
                (ashift:TI (reg:TI 329)
                    (reg:QI 521)))
            (clobber (reg:CC 17 flags))
        ]) "test.c":11:13 953 {ashlti3_doubleword}

is reloaded into

(insn 98 452 387 2 (parallel [
            (set (reg:TI 0 ax [orig:337 _32 ] [337])
                (ashift:TI (const_int 1671291085 [0x639de0cd])
                    (reg:QI 2 cx [521])))
            (clobber (reg:CC 17 flags))

since constraint n in the pattern accepts that.
(Not sure why reload doesn't check predicate)

(define_insn "ashl<mode>3_doubleword"
  [(set (match_operand:DWI 0 "register_operand" "=&r,&r")
        (ashift:DWI (match_operand:DWI 1 "reg_or_pm1_operand" "0n,r")
                    (match_operand:QI 2 "nonmemory_operand" "<S>c,<S>c")))

The patch fixes the mismatch between constraint and predicate.

Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
Ok for trunk?

gcc/ChangeLog:

	PR target/116096
	* config/i386/constraints.md (BC): Move TARGET_SSE to
	vector_all_ones_operand.
	* config/i386/i386.md (ashl<mode>3_doubleword): Refine
	constraint with BC.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/pr116096.c: New test.
---
 gcc/config/i386/constraints.md           |  4 ++--
 gcc/config/i386/i386.md                  |  2 +-
 gcc/testsuite/gcc.target/i386/pr116096.c | 26 ++++++++++++++++++++++++
 3 files changed, 29 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/pr116096.c

Comments

Hongtao Liu July 26, 2024, 7:06 a.m. UTC | #1 
On Fri, Jul 26, 2024 at 2:59 PM liuhongt <hongtao.liu@intel.com> wrote:
>
> (insn 98 94 387 2 (parallel [
>             (set (reg:TI 337 [ _32 ])
>                 (ashift:TI (reg:TI 329)
>                     (reg:QI 521)))
>             (clobber (reg:CC 17 flags))
>         ]) "test.c":11:13 953 {ashlti3_doubleword}
>
> is reloaded into
>
> (insn 98 452 387 2 (parallel [
>             (set (reg:TI 0 ax [orig:337 _32 ] [337])
>                 (ashift:TI (const_int 1671291085 [0x639de0cd])
>                     (reg:QI 2 cx [521])))
>             (clobber (reg:CC 17 flags))
>
> since constraint n in the pattern accepts that.
> (Not sure why reload doesn't check predicate)
>
> (define_insn "ashl<mode>3_doubleword"
>   [(set (match_operand:DWI 0 "register_operand" "=&r,&r")
>         (ashift:DWI (match_operand:DWI 1 "reg_or_pm1_operand" "0n,r")
>                     (match_operand:QI 2 "nonmemory_operand" "<S>c,<S>c")))
>
> The patch fixes the mismatch between constraint and predicate.
>
> Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
> Ok for trunk?
Please ignore this, I need to support 1 in the constraint.
>
> gcc/ChangeLog:
>
>         PR target/116096
>         * config/i386/constraints.md (BC): Move TARGET_SSE to
>         vector_all_ones_operand.
>         * config/i386/i386.md (ashl<mode>3_doubleword): Refine
>         constraint with BC.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/i386/pr116096.c: New test.
> ---
>  gcc/config/i386/constraints.md           |  4 ++--
>  gcc/config/i386/i386.md                  |  2 +-
>  gcc/testsuite/gcc.target/i386/pr116096.c | 26 ++++++++++++++++++++++++
>  3 files changed, 29 insertions(+), 3 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/i386/pr116096.c
>
> diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md
> index 7508d7a58bd..fd032c2b9f0 100644
> --- a/gcc/config/i386/constraints.md
> +++ b/gcc/config/i386/constraints.md
> @@ -225,8 +225,8 @@ (define_constraint "Bz"
>
>  (define_constraint "BC"
>    "@internal integer SSE constant with all bits set operand."
> -  (and (match_test "TARGET_SSE")
> -       (ior (match_test "op == constm1_rtx")
> +  (ior (match_test "op == constm1_rtx")
> +       (and (match_test "TARGET_SSE")
>             (match_operand 0 "vector_all_ones_operand"))))
>
>  (define_constraint "BF"
> diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
> index 6207036a2a0..9c4e847fba1 100644
> --- a/gcc/config/i386/i386.md
> +++ b/gcc/config/i386/i386.md
> @@ -14774,7 +14774,7 @@ (define_insn_and_split "*ashl<dwi>3_doubleword_mask_1"
>
>  (define_insn "ashl<mode>3_doubleword"
>    [(set (match_operand:DWI 0 "register_operand" "=&r,&r")
> -       (ashift:DWI (match_operand:DWI 1 "reg_or_pm1_operand" "0n,r")
> +       (ashift:DWI (match_operand:DWI 1 "reg_or_pm1_operand" "0BC,r")
>                     (match_operand:QI 2 "nonmemory_operand" "<S>c,<S>c")))
>     (clobber (reg:CC FLAGS_REG))]
>    ""
> diff --git a/gcc/testsuite/gcc.target/i386/pr116096.c b/gcc/testsuite/gcc.target/i386/pr116096.c
> new file mode 100644
> index 00000000000..5ef39805f58
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr116096.c
> @@ -0,0 +1,26 @@
> +/* { dg-do compile { target int128 } } */
> +/* { dg-options "-O2 -flive-range-shrinkage -fno-peephole2 -mstackrealign -Wno-psabi" } */
> +
> +typedef char U __attribute__((vector_size (32)));
> +typedef unsigned V __attribute__((vector_size (32)));
> +typedef __int128 W __attribute__((vector_size (32)));
> +U g;
> +
> +W baz ();
> +
> +static inline U
> +bar (V x, W y)
> +{
> +  y = y | y << (W) x;
> +  return (U)y;
> +}
> +
> +void
> +foo (W w)
> +{
> +  g = g <<
> +    bar ((V){baz ()[1], 3, 3, 5, 7},
> +        (W){w[0], ~(int) 2623676210}) >>
> +    bar ((V){baz ()[1]},
> +        (W){-w[0], ~(int) 2623676210});
> +}
> --
> 2.31.1
>
diff mbox series

Patch

diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md
index 7508d7a58bd..fd032c2b9f0 100644
--- a/gcc/config/i386/constraints.md
+++ b/gcc/config/i386/constraints.md
@@ -225,8 +225,8 @@  (define_constraint "Bz"
 
 (define_constraint "BC"
   "@internal integer SSE constant with all bits set operand."
-  (and (match_test "TARGET_SSE")
-       (ior (match_test "op == constm1_rtx")
+  (ior (match_test "op == constm1_rtx")
+       (and (match_test "TARGET_SSE")
 	    (match_operand 0 "vector_all_ones_operand"))))
 
 (define_constraint "BF"
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 6207036a2a0..9c4e847fba1 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -14774,7 +14774,7 @@  (define_insn_and_split "*ashl<dwi>3_doubleword_mask_1"
 
 (define_insn "ashl<mode>3_doubleword"
   [(set (match_operand:DWI 0 "register_operand" "=&r,&r")
-	(ashift:DWI (match_operand:DWI 1 "reg_or_pm1_operand" "0n,r")
+	(ashift:DWI (match_operand:DWI 1 "reg_or_pm1_operand" "0BC,r")
 		    (match_operand:QI 2 "nonmemory_operand" "<S>c,<S>c")))
    (clobber (reg:CC FLAGS_REG))]
   ""
diff --git a/gcc/testsuite/gcc.target/i386/pr116096.c b/gcc/testsuite/gcc.target/i386/pr116096.c
new file mode 100644
index 00000000000..5ef39805f58
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr116096.c
@@ -0,0 +1,26 @@ 
+/* { dg-do compile { target int128 } } */
+/* { dg-options "-O2 -flive-range-shrinkage -fno-peephole2 -mstackrealign -Wno-psabi" } */
+
+typedef char U __attribute__((vector_size (32)));
+typedef unsigned V __attribute__((vector_size (32)));
+typedef __int128 W __attribute__((vector_size (32)));
+U g;
+
+W baz ();
+
+static inline U
+bar (V x, W y)
+{
+  y = y | y << (W) x;
+  return (U)y;
+}
+
+void
+foo (W w)
+{
+  g = g <<
+    bar ((V){baz ()[1], 3, 3, 5, 7},
+	 (W){w[0], ~(int) 2623676210}) >>
+    bar ((V){baz ()[1]},
+	 (W){-w[0], ~(int) 2623676210});
+}