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Thu, 25 Jul 2024 15:55:33 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA02.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 46PFtW7N007538 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 25 Jul 2024 15:55:32 GMT Received: from hu-apinski-lv.qualcomm.com (10.49.16.6) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 25 Jul 2024 08:55:32 -0700 From: Andrew Pinski To: CC: Andrew Pinski Subject: [PATCH] MATCH: Optimize `VEC_SHL_INSERT (dup (A), A)` to just `dup (A) [PR116075] Date: Thu, 25 Jul 2024 08:55:16 -0700 Message-ID: <20240725155516.3965022-1-quic_apinski@quicinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: dQnDPII02C4FzOCIEv6pJ5axLtrSHZ7G X-Proofpoint-ORIG-GUID: dQnDPII02C4FzOCIEv6pJ5axLtrSHZ7G X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-25_14,2024-07-25_03,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 lowpriorityscore=0 spamscore=0 mlxscore=0 clxscore=1015 suspectscore=0 adultscore=0 impostorscore=0 bulkscore=0 phishscore=0 mlxlogscore=995 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407250109 X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org It was noticed if we have `.VEC_SHL_INSERT ({ 0, ... }, 0)` it was not being simplified to just `{ 0, ... }`. This was generated from the autovectorizer (maybe even on accident, see PR tree-optmization/116081). This adds a few SVE testcases to see if this is optimized since the auto-vectorizer or intrinsics are the only two ways of getting this produced. Build and tested for aarch64-linux-gnu with no regressions. PR target/116075 gcc/ChangeLog: * match.pd (`VEC_SHL_INSERT (dup (A), A)`): New pattern. gcc/testsuite/ChangeLog: * gcc.target/aarch64/sve/dup-insr-1.c: New test. * gcc.target/aarch64/sve/dup-insr-2.c: New test. Signed-off-by: Andrew Pinski --- gcc/match.pd | 17 ++++++++++++ .../gcc.target/aarch64/sve/dup-insr-1.c | 26 +++++++++++++++++++ .../gcc.target/aarch64/sve/dup-insr-2.c | 26 +++++++++++++++++++ 3 files changed, 69 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/dup-insr-1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/dup-insr-2.c diff --git a/gcc/match.pd b/gcc/match.pd index 680dfea523f..a3a64bd742e 100644 --- a/gcc/match.pd +++ b/gcc/match.pd @@ -10657,3 +10657,20 @@ and, } (if (full_perm_p) (vec_perm (op@3 @0 @1) @3 @2)))))) + +/* vec shift left insert (dup(A), A) -> dup(A) */ +(simplify + (IFN_VEC_SHL_INSERT vec_same_elem_p@0 @1) + (with { + tree elem = uniform_vector_p (@0); + if (!elem && TREE_CODE (@0) == SSA_NAME) + { + gimple *def = SSA_NAME_DEF_STMT (@0); + if (gimple_assign_rhs_code (def) == CONSTRUCTOR) + elem = uniform_vector_p (gimple_assign_rhs1 (def)); + else if (gimple_assign_rhs_code (def) == VEC_DUPLICATE_EXPR) + elem = gimple_assign_rhs1 (def); + } + } + (if (elem && operand_equal_p (@1, elem)) + @0))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/dup-insr-1.c b/gcc/testsuite/gcc.target/aarch64/sve/dup-insr-1.c new file mode 100644 index 00000000000..41dcbba45cf --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/dup-insr-1.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-O -fdump-tree-optimized" } */ +/* PR target/116075 */ + +#include + +svint8_t f(void) +{ + svint8_t tt; + tt = svdup_s8 (0); + tt = svinsr (tt, 0); + return tt; +} + +svint8_t f1(int8_t t) +{ + svint8_t tt; + tt = svdup_s8 (t); + tt = svinsr (tt, t); + return tt; +} + +/* The above 2 functions should have removed the VEC_SHL_INSERT. */ + +/* { dg-final { scan-tree-dump-not ".VEC_SHL_INSERT " "optimized" } } */ + diff --git a/gcc/testsuite/gcc.target/aarch64/sve/dup-insr-2.c b/gcc/testsuite/gcc.target/aarch64/sve/dup-insr-2.c new file mode 100644 index 00000000000..8eafe974624 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/dup-insr-2.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-O -fdump-tree-optimized" } */ +/* PR target/116075 */ + +#include + +svint8_t f(int8_t t) +{ + svint8_t tt; + tt = svdup_s8 (0); + tt = svinsr (tt, t); + return tt; +} + +svint8_t f1(int8_t t) +{ + svint8_t tt; + tt = svdup_s8 (t); + tt = svinsr (tt, 0); + return tt; +} + +/* The above 2 functions should not have removed the VEC_SHL_INSERT. */ + +/* { dg-final { scan-tree-dump-times ".VEC_SHL_INSERT " 2 "optimized" } } */ +