From patchwork Thu Jul 25 02:14:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Pinski X-Patchwork-Id: 1964585 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=quicinc.com header.i=@quicinc.com header.a=rsa-sha256 header.s=qcppdkim1 header.b=oGRgg0zR; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4WTvgB0DfFz1ybY for ; Thu, 25 Jul 2024 12:17:58 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 560133858430 for ; Thu, 25 Jul 2024 02:17:56 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by sourceware.org (Postfix) with ESMTPS id EB3903858402 for ; Thu, 25 Jul 2024 02:15:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EB3903858402 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=quicinc.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org EB3903858402 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1721873711; cv=none; b=jxiNxRYkRTF8sIJOfuhokT4DXvO9KRGwrHOZ4uXcY3U0BjX+07Tg4cdFn4vSnC4O8YgAt2EAMJcrEBsJf1DVlARcbnhAbzyoMrscDgvS+zELIqaNoycIwrM8O6NJnpzZSd/gjNjuUdYXk3g6CYntA6mlzTNquh3QTtsCEqpHNM4= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1721873711; c=relaxed/simple; bh=lMGM/JSSycX/KQnpV2cUnHiAGVZOJ/39evai+4exUQc=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=gB4iMTW3VMC4kBi84NtUYXRkFKiL6xqPPTGIvkCkowJuDPiL0kO4JLaieIBuekAHm0fbFTcSF/FxLHCEkXMJQc8wQ4MhoVEKkiNPt/GM33IPPOrLhHDAaUyVLooCHfA33TcDgjsrRKlR34n3ANPDvWifQh/tlS/mU2WWp5WSDjw= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 46OL3ujK002530 for ; Thu, 25 Jul 2024 02:15:08 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= /dnR+3kzYvni/TTfEx3HgUSsXwwWuGJBVxty0fWU3ds=; b=oGRgg0zRNsXGPD+F A83mPuu+n16PazWDm6liis4dJvhYr6AfgL6uWvNX2F1QaVeOEEy00ACP2qkLfjAU yS9YDeD7nvPnExI2PHauuv40TnejZV/d/lcQ3sNEsc8ma4w/E5XFiRa7DMG/VlmA i8o7qgg6qOfDhyLONKml2q0Qm0FXuj0FU33QUUMFcO7x6KJtVjzMe6xUa6KtV1t7 SZhqhO1GZQhzzYFR8z+k5GZUAV36ZwQYd8czUAxqU6sAGfz4yL7ysjiyOEWUp2Hf AaNCxSEEwaQaho4tid+7hTk/OSmASui0IF5Jpke45l5vRZ7Lp9oa0Sm+P3sJDpTP O0eigA== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 40gurtt7pg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 25 Jul 2024 02:15:08 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA01.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 46P2F7hD025184 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 25 Jul 2024 02:15:07 GMT Received: from hu-apinski-lv.qualcomm.com (10.49.16.6) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 24 Jul 2024 19:15:06 -0700 From: Andrew Pinski To: CC: Andrew Pinski Subject: [PATCH 5/5] MATCH: Add an alt pattern for ANDN and IORN with constants Date: Wed, 24 Jul 2024 19:14:49 -0700 Message-ID: <20240725021449.3650437-5-quic_apinski@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240725021449.3650437-1-quic_apinski@quicinc.com> References: <20240725021449.3650437-1-quic_apinski@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: k6c89yPHIBqaDv0WLelv68p6sieNanq0 X-Proofpoint-ORIG-GUID: k6c89yPHIBqaDv0WLelv68p6sieNanq0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-25_02,2024-07-24_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 phishscore=0 adultscore=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 impostorscore=0 mlxlogscore=999 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407250012 X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org With constants we can match `~(a | CST)` into `CST & ~a`. Likewise `~(a & CST)` into `CST | ~a`. Built and tested for aarch64-linux-gnu with no regressions. PR target/116013 PR target/115086 gcc/ChangeLog: * match.pd (`~(a & CST)`, `~(a | CST)`): New pattern. gcc/testsuite/ChangeLog: * gcc.target/aarch64/bic-cst-2.c: New test. * gcc.target/aarch64/bic_simd-2.c: New test. Signed-off-by: Andrew Pinski --- gcc/match.pd | 10 ++++++ gcc/testsuite/gcc.target/aarch64/bic-cst-2.c | 31 +++++++++++++++++ gcc/testsuite/gcc.target/aarch64/bic_simd-2.c | 33 +++++++++++++++++++ 3 files changed, 74 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/bic-cst-2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/bic_simd-2.c diff --git a/gcc/match.pd b/gcc/match.pd index 56f631dfeec..680dfea523f 100644 --- a/gcc/match.pd +++ b/gcc/match.pd @@ -9994,6 +9994,16 @@ and, (simplify (bitopc @0 CONSTANT_CLASS_P@1) (bitop (bit_not! @1) @0))) + +/* Create bit_andc and bit_iorc internal functions. */ +(for rbitop (bit_ior bit_and) + bitopc (IFN_BIT_ANDN IFN_BIT_IORN) + (simplify + (bit_not (rbitop:s @0 CONSTANT_CLASS_P@1)) + (if (canonicalize_math_after_vectorization_p () + && direct_internal_fn_supported_p (as_internal_fn (bitopc), + type, OPTIMIZE_FOR_BOTH)) + (bitopc (bit_not! @1) @0)))) #endif /* For pointers @0 and @2 and nonnegative constant offset @1, look for diff --git a/gcc/testsuite/gcc.target/aarch64/bic-cst-2.c b/gcc/testsuite/gcc.target/aarch64/bic-cst-2.c new file mode 100644 index 00000000000..b89ac72dae1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/bic-cst-2.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -fdump-tree-optimized" } */ +/* { dg-final { check-function-bodies "**" "" "" { target { le } } } } */ + +/** +**bar1: +** mov w([0-9]+), 4 +** bic w0, w\1, w1 +** ret +*/ +int bar1(int a, int c) +{ + int b = ~((~4) | c); + return b; +} + +/** +**foo1: +** mov w([0-9]+), 4 +** orn w0, w\1, w1 +** ret +*/ +int foo1(int a, int c) +{ + int b = ~((~4) & c); + return b; +} + +/* { dg-final { scan-tree-dump ".BIT_ANDN " "optimized" } } */ +/* { dg-final { scan-tree-dump ".BIT_IORN " "optimized" } } */ + diff --git a/gcc/testsuite/gcc.target/aarch64/bic_simd-2.c b/gcc/testsuite/gcc.target/aarch64/bic_simd-2.c new file mode 100644 index 00000000000..8543ce61400 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/bic_simd-2.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -fdump-tree-optimized" } */ +/* { dg-final { check-function-bodies "**" "" "" { target { le } } } } */ + +/** +**bar1: +** movi v([0-9]+).2s, 0x4 +** bic v0.8b, v\1.8b, v1.8b +** ret +*/ +#define vect8 __attribute__((vector_size(8))) +vect8 int bar1(vect8 int a, vect8 int c) +{ + vect8 int b = ~((~4) | c); + return b; +} + +/** +**foo1: +** movi v([0-9]+).2s, 0x4 +** orn v0.8b, v\1.8b, v1.8b +** ret +*/ +#define vect8 __attribute__((vector_size(8))) +vect8 int foo1(vect8 int a, vect8 int c) +{ + vect8 int b = ~((~4) & c); + return b; +} + +/* { dg-final { scan-tree-dump ".BIT_ANDN " "optimized" } } */ +/* { dg-final { scan-tree-dump ".BIT_IORN " "optimized" } } */ +