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[3/5] aarch64: Use iorn and andn standard pattern names for scalar modes

Message ID 20240725021449.3650437-3-quic_apinski@quicinc.com
State New
Headers show
Series [1/5] aarch64: Rename bic/orn patterns to iorn/andn for vector modes | expand

Commit Message

Andrew Pinski July 25, 2024, 2:14 a.m. UTC
Since r15-1890-gf379596e0ba99d, these are the new optabs.
So let's use these names for them. These will be used to
generate during expand from gimple in the next few patches.

Built and tested for aarch64-linux-gnu with no regressions.

gcc/ChangeLog:

	* config/aarch64/aarch64.md (*<NLOGICAL:optab>_one_cmpl<mode>3): Rename to ...
	(<NLOGICAL:optab>n<mode>3): This.
	(*<NLOGICAL:optab>_one_cmplsidi3_ze): Rename to ...
	(*<NLOGICAL:optab>nsidi3_ze): this.

Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
---
 gcc/config/aarch64/aarch64.md | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

Comments

Kyrylo Tkachov July 25, 2024, 6:26 a.m. UTC | #1
Hi Andrew,

> On 25 Jul 2024, at 04:14, Andrew Pinski <quic_apinski@quicinc.com> wrote:
> 
> External email: Use caution opening links or attachments
> 
> 
> Since r15-1890-gf379596e0ba99d, these are the new optabs.
> So let's use these names for them. These will be used to
> generate during expand from gimple in the next few patches.
> 
> Built and tested for aarch64-linux-gnu with no regressions.
> 
> gcc/ChangeLog:
> 
>        * config/aarch64/aarch64.md (*<NLOGICAL:optab>_one_cmpl<mode>3): Rename to ...
>        (<NLOGICAL:optab>n<mode>3): This.
>        (*<NLOGICAL:optab>_one_cmplsidi3_ze): Rename to ...
>        (*<NLOGICAL:optab>nsidi3_ze): this.

Should be uppercase “This.”
Ok.
Thanks,
Kyrill

> 
> Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
> ---
> gcc/config/aarch64/aarch64.md | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
> index 94ff0eefa77..ed29127dafb 100644
> --- a/gcc/config/aarch64/aarch64.md
> +++ b/gcc/config/aarch64/aarch64.md
> @@ -5069,18 +5069,18 @@ (define_insn "*one_cmpl_<optab><mode>2"
> 
> ;; Binary logical operators negating one operand, i.e. (a & !b), (a | !b).
> 
> -(define_insn "*<NLOGICAL:optab>_one_cmpl<mode>3"
> +(define_insn "<NLOGICAL:optab>n<mode>3"
>   [(set (match_operand:GPI 0 "register_operand")
> -       (NLOGICAL:GPI (not:GPI (match_operand:GPI 1 "register_operand"))
> -                    (match_operand:GPI 2 "register_operand")))]
> +       (NLOGICAL:GPI (not:GPI (match_operand:GPI 2 "register_operand"))
> +                    (match_operand:GPI 1 "register_operand")))]
>   ""
>   {@ [ cons: =0 , 1 , 2 ; attrs: type , arch  ]
> -     [ r        , r , r ; logic_reg   , *     ] <NLOGICAL:nlogical>\t%<w>0, %<w>2, %<w>1
> -     [ w        , w , w ; neon_logic  , simd  ] <NLOGICAL:nlogical>\t%0.<Vbtype>, %2.<Vbtype>, %1.<Vbtype>
> +     [ r        , r , r ; logic_reg   , *     ] <NLOGICAL:nlogical>\t%<w>0, %<w>1, %<w>2
> +     [ w        , w , w ; neon_logic  , simd  ] <NLOGICAL:nlogical>\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>
>   }
> )
> 
> -(define_insn "*<NLOGICAL:optab>_one_cmplsidi3_ze"
> +(define_insn "*<NLOGICAL:optab>nsidi3_ze"
>   [(set (match_operand:DI 0 "register_operand" "=r")
>        (zero_extend:DI
>          (NLOGICAL:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
> --
> 2.43.0
>
diff mbox series

Patch

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 94ff0eefa77..ed29127dafb 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -5069,18 +5069,18 @@  (define_insn "*one_cmpl_<optab><mode>2"
 
 ;; Binary logical operators negating one operand, i.e. (a & !b), (a | !b).
 
-(define_insn "*<NLOGICAL:optab>_one_cmpl<mode>3"
+(define_insn "<NLOGICAL:optab>n<mode>3"
   [(set (match_operand:GPI 0 "register_operand")
-	(NLOGICAL:GPI (not:GPI (match_operand:GPI 1 "register_operand"))
-		     (match_operand:GPI 2 "register_operand")))]
+	(NLOGICAL:GPI (not:GPI (match_operand:GPI 2 "register_operand"))
+		     (match_operand:GPI 1 "register_operand")))]
   ""
   {@ [ cons: =0 , 1 , 2 ; attrs: type , arch  ]
-     [ r        , r , r ; logic_reg   , *     ] <NLOGICAL:nlogical>\t%<w>0, %<w>2, %<w>1
-     [ w        , w , w ; neon_logic  , simd  ] <NLOGICAL:nlogical>\t%0.<Vbtype>, %2.<Vbtype>, %1.<Vbtype>
+     [ r        , r , r ; logic_reg   , *     ] <NLOGICAL:nlogical>\t%<w>0, %<w>1, %<w>2
+     [ w        , w , w ; neon_logic  , simd  ] <NLOGICAL:nlogical>\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>
   }
 )
 
-(define_insn "*<NLOGICAL:optab>_one_cmplsidi3_ze"
+(define_insn "*<NLOGICAL:optab>nsidi3_ze"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(zero_extend:DI
 	  (NLOGICAL:SI (not:SI (match_operand:SI 1 "register_operand" "r"))