From patchwork Wed Jul 24 02:39:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jiawei X-Patchwork-Id: 1964106 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4WTJCQ67WLz1yZw for ; Wed, 24 Jul 2024 12:40:18 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id AE3913858429 for ; Wed, 24 Jul 2024 02:40:16 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp81.cstnet.cn [159.226.251.81]) by sourceware.org (Postfix) with ESMTPS id 4C9693858D29 for ; Wed, 24 Jul 2024 02:39:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4C9693858D29 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 4C9693858D29 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=159.226.251.81 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1721788794; cv=none; b=K//G0ULD9XwDCDSGp65oeiVb4sadOsibG6TD3hhnMBLuCPFGleG5umv/mo6mQiS41qdkvQeSiZ79BNnLGMX0BIQDQ7zkLw+256Yvt/i5Zr5PD47HytV9K+CIjKWtxuWmOwlTlQktAXsKnUY/IgWmv6xSXyXodZiisfFTKclB86c= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1721788794; c=relaxed/simple; bh=5a0ABLrJW5aMxbNs8CTz0LilLl1qdAavxfS+0BHnldk=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=XW8XpItXn+S0SZp7E20/6xqBcgeeNv1kSfYmAymToMWMVHecEiW9WWwKB71J7xYQdEFD9DTw7txWLR6wO0z5bQZDS0ZeOLes8GzAP1RL7rQCzHv2Kg5plk+YzLS8z7EgAZKsuHfEI+7oNBt8psW9zPe4BiWA7RxVPWm/XS2dCGs= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from localhost.localdomain (unknown [112.74.111.65]) by APP-03 (Coremail) with SMTP id rQCowAB3nwJvaaBmCcqxAA--.41415S2; Wed, 24 Jul 2024 10:39:44 +0800 (CST) From: Jiawei To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, jlaw@ventanamicro.com, christoph.muellner@vrull.eu, palmer@rivosinc.com, Jiawei Subject: [PATCH v3] RISC-V: Supports Profiles in '-march' option. Date: Wed, 24 Jul 2024 10:39:30 +0800 Message-Id: <20240724023930.4549-1-jiawei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CM-TRANSID: rQCowAB3nwJvaaBmCcqxAA--.41415S2 X-Coremail-Antispam: 1UD129KBjvJXoW3Xw18uF4kZry5CF17Kr1Dtrb_yoWxZr1DpF W5C39YkrZ5ZF92gryftr1UWw43Kr93WrWYvwn29ryUCayDJrWrXF1kKw1fCF15JF48ur13 ur4UuryFvw45X3DanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUkK14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4j 6F4UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gr 1j6F4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv 7VC0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r 1j6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY1x0262kKe7AK xVWUAVWUtwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F4 0E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw1l IxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxV AFwI0_Jr0_Gr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j 6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Jr0_GrUvcSsGvfC2KfnxnUUI43ZEXa7VUjuHq7 UUUUU== X-Originating-IP: [112.74.111.65] X-CM-SenderInfo: 5mld4v3l6l2u1dvotugofq/1tbiBgsIAGagL0awnQAAsH X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Supports RISC-V profiles[1] in -march option. Default input set the profile before other formal extensions. V2: Fixes some format errors and adds code comments for parse function Thanks for Jeff Law's review and comments. V3: Update testcases and profiles extensions support.Remove S/M mode Profiles. Thanks for Christoph Müllner,Palmer Dabbelt's review and comments. [1]https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc --- gcc/common/config/riscv/riscv-common.cc | 71 +++++++++++++++++++++++- gcc/config/riscv/riscv-subset.h | 2 + gcc/testsuite/gcc.target/riscv/arch-41.c | 5 ++ gcc/testsuite/gcc.target/riscv/arch-42.c | 12 ++++ gcc/testsuite/gcc.target/riscv/arch-43.c | 12 ++++ 5 files changed, 101 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/arch-41.c create mode 100644 gcc/testsuite/gcc.target/riscv/arch-42.c create mode 100644 gcc/testsuite/gcc.target/riscv/arch-43.c diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 682826c0e34..e092026fe9b 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -231,6 +231,12 @@ struct riscv_ext_version int minor_version; }; +struct riscv_profiles +{ + const char *profile_name; + const char *profile_string; +}; + /* All standard extensions defined in all supported ISA spec. */ static const struct riscv_ext_version riscv_ext_version_table[] = { @@ -442,6 +448,31 @@ static const struct riscv_ext_version riscv_combine_info[] = {NULL, ISA_SPEC_CLASS_NONE, 0, 0} }; +/* This table records the mapping form RISC-V Profiles into march string. */ +static const riscv_profiles riscv_profiles_table[] = +{ + /* RVI20U only contains the base extension 'i' as mandatory extension. */ + {"RVI20U64", "rv64i"}, + {"RVI20U32", "rv32i"}, + + /* RVA20U contains the 'i,m,a,f,d,c,zicsr,zicntr,ziccif,ziccrse,ziccamoa, + zicclsm,za128rs' as mandatory extensions. */ + {"RVA20U64", "rv64imafdc_zicsr_zicntr_ziccif_ziccrse_ziccamoa" + "_zicclsm_za128rs"}, + + /* RVA22U contains the 'i,m,a,f,d,c,zicsr,zihintpause,zba,zbb,zbs,zicntr, + zihpm,ziccif,ziccrse,ziccamoa, zicclsm,zic64b,za64rs,zicbom,zicbop,zicboz, + zfhmin,zkt' as mandatory extensions. */ + {"RVA22U64", "rv64imafdc_zicsr_zicntr_ziccif_ziccrse_ziccamoa" + "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop" + "_zicboz_zfhmin_zkt"}, + + /* Currently we do not define S/M mode Profiles in gcc part. */ + + /* Terminate the list. */ + {NULL, NULL} +}; + static const riscv_cpu_info riscv_cpu_tables[] = { #define RISCV_CORE(CORE_NAME, ARCH, TUNE) \ @@ -1047,6 +1078,42 @@ riscv_subset_list::parsing_subset_version (const char *ext, return p; } +/* Parsing RISC-V Profiles in -march string. + Return string with mandatory extensions of Profiles. */ +const char * +riscv_subset_list::parse_profiles (const char * p){ + /* Checking if input string contains a Profiles. + There are two cases use Profiles in -march option + + 1. Only use Profiles as -march input + 2. Mixed Profiles with other extensions + + use '+' to split Profiles and other extension. */ + for (int i = 0; riscv_profiles_table[i].profile_name != NULL; ++i) { + const char* match = strstr(p, riscv_profiles_table[i].profile_name); + const char* plus_ext = strchr(p, '+'); + /* Find profile at the begin. */ + if (match != NULL && match == p) { + /* If there's no '+' sign, return the profile_string directly. */ + if(!plus_ext) + return riscv_profiles_table[i].profile_string; + /* If there's a '+' sign, need to add profiles with other ext. */ + else { + size_t arch_len = strlen(riscv_profiles_table[i].profile_string)+ + strlen(plus_ext); + /* Reset the input string with Profiles mandatory extensions, + end with '_' to connect other additional extensions. */ + char* result = new char[arch_len + 2]; + strcpy(result, riscv_profiles_table[i].profile_string); + strcat(result, "_"); + strcat(result, plus_ext + 1); /* skip the '+'. */ + return result; + } + } + } + return p; +} + /* Parsing function for base extensions, rv[32|64][i|e|g] Return Value: @@ -1060,6 +1127,8 @@ riscv_subset_list::parse_base_ext (const char *p) unsigned major_version = 0; unsigned minor_version = 0; bool explicit_version_p = false; + + p = parse_profiles(p); if (startswith (p, "rv32")) { @@ -1073,7 +1142,7 @@ riscv_subset_list::parse_base_ext (const char *p) } else { - error_at (m_loc, "%<-march=%s%>: ISA string must begin with rv32 or rv64", + error_at (m_loc, "%<-march=%s%>: ISA string must begin with rv32, rv64 or Profile", m_arch); return NULL; } diff --git a/gcc/config/riscv/riscv-subset.h b/gcc/config/riscv/riscv-subset.h index dace4de6575..98fd9877f74 100644 --- a/gcc/config/riscv/riscv-subset.h +++ b/gcc/config/riscv/riscv-subset.h @@ -80,6 +80,8 @@ private: const char *parse_single_multiletter_ext (const char *, const char *, const char *, bool); + const char *parse_profiles (const char*); + void handle_implied_ext (const char *); bool check_implied_ext (); void handle_combine_ext (); diff --git a/gcc/testsuite/gcc.target/riscv/arch-41.c b/gcc/testsuite/gcc.target/riscv/arch-41.c new file mode 100644 index 00000000000..41190bc5939 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-41.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=RVI20U64 -mabi=lp64" } */ +int +foo () +{} diff --git a/gcc/testsuite/gcc.target/riscv/arch-42.c b/gcc/testsuite/gcc.target/riscv/arch-42.c new file mode 100644 index 00000000000..273c6abf60d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-42.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=RVI20U64+mafdc -mabi=lp64d" } */ +#if !(defined __riscv_mul) || \ + !(defined __riscv_atomic) || \ + !(defined __riscv_flen) || \ + !(defined __riscv_div) || \ + !(defined __riscv_compressed) +#error "Feature macros not defined" +#endif +int +foo () +{} diff --git a/gcc/testsuite/gcc.target/riscv/arch-43.c b/gcc/testsuite/gcc.target/riscv/arch-43.c new file mode 100644 index 00000000000..1ebf50d3755 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-43.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=RVA20U64 -mabi=lp64d" } */ +#if !(defined __riscv_mul) || \ + !(defined __riscv_atomic) || \ + !(defined __riscv_flen) || \ + !(defined __riscv_div) || \ + !(defined __riscv_compressed) +#error "Feature macros not defined" +#endif +int +foo () +{}