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Thu, 18 Jul 2024 15:23:19 +0800 X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.164 From: MayShao-oc X-Barracuda-RBL-Trusted-Forwarder: 10.29.252.6 To: CC: , , , , Subject: [PATCH v2] [libatomic]: Handle AVX+CX16 ZHAOXIN like intel for 16b atomic [PR104688] Date: Thu, 18 Jul 2024 15:23:05 +0800 X-ASG-Orig-Subj: [PATCH v2] [libatomic]: Handle AVX+CX16 ZHAOXIN like intel for 16b atomic [PR104688] Message-ID: <20240718072305.3609-1-MayShao-oc@zhaoxin.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [114.254.3.138] X-ClientProxiedBy: ZXSHCAS1.zhaoxin.com (10.28.252.161) To ZXBJMBX02.zhaoxin.com (10.29.252.6) X-Barracuda-Connect: ZXSHMBX2.zhaoxin.com[10.28.252.164] X-Barracuda-Start-Time: 1721287401 X-Barracuda-Encrypted: ECDHE-RSA-AES128-GCM-SHA256 X-Barracuda-URL: https://10.28.252.35:4443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 1599 X-Barracuda-BRTS-Status: 1 X-Barracuda-Bayes: INNOCENT GLOBAL 0.0000 1.0000 -2.0210 X-Barracuda-Spam-Score: -2.02 X-Barracuda-Spam-Status: No, SCORE=-2.02 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.127786 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: mayshao Hi Jakub: Thanks for your review,We should just amend this to handle Zhaoxin. Bootstrapped /regtested X86_64. Ok for trunk? BR Mayshao libatomic/ChangeLog: PR target/104688 * config/x86/init.c (__libat_feat1_init): Don't clear bit_AVX on ZHAOXIN CPUs. --- libatomic/config/x86/init.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/libatomic/config/x86/init.c b/libatomic/config/x86/init.c index a75be3f175c..0d6864909bb 100644 --- a/libatomic/config/x86/init.c +++ b/libatomic/config/x86/init.c @@ -39,12 +39,15 @@ __libat_feat1_init (void) == (bit_AVX | bit_CMPXCHG16B)) { /* Intel SDM guarantees that 16-byte VMOVDQA on 16-byte aligned address - is atomic, and AMD is going to do something similar soon. - We don't have a guarantee from vendors of other CPUs with AVX, - like Zhaoxin and VIA. */ - unsigned int ecx2 = 0; + is atomic, and AMD is going to do something similar soon. Zhaoxin also + guarantees this. We don't have a guarantee from vendors of other CPUs + with AVX,like VIA. */ + unsigned int ecx2 = 0, family = 0; + family = (eax >> 8) & 0x0f; __get_cpuid (0, &eax, &ebx, &ecx2, &edx); - if (ecx2 != signature_INTEL_ecx && ecx2 != signature_AMD_ecx) + if (ecx2 != signature_INTEL_ecx && ecx2 != signature_AMD_ecx + && !(ecx2 == signature_CENTAUR_ecx && family > 0x6) + && ecx2 != signature_SHANGHAI_ecx) FEAT1_REGISTER &= ~bit_AVX; } #endif