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X-CSE-ConnectionGUID: e7TUMLINRWi/dUGuw5FpNw== X-CSE-MsgGUID: 3g0j5cQmRjWwmyRhSaCB1A== X-IronPort-AV: E=McAfee;i="6700,10204,11136"; a="18628451" X-IronPort-AV: E=Sophos;i="6.09,216,1716274800"; d="scan'208";a="18628451" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jul 2024 21:19:23 -0700 X-CSE-ConnectionGUID: ewlSpqAhTBOUUrgNUq93EQ== X-CSE-MsgGUID: qmiYZchISs+ovxPDYpVgWg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,216,1716274800"; d="scan'208";a="88106093" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orviesa001.jf.intel.com with ESMTP; 17 Jul 2024 21:19:20 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 3E7D6100735A; Thu, 18 Jul 2024 12:19:19 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, richard.guenther@gmail.com, tamar.christina@arm.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v1] Doc: Add Standard-Names ustrunc and sstrunc for integer modes Date: Thu, 18 Jul 2024 12:19:13 +0800 Message-Id: <20240718041913.1050890-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li This patch would like to add the doc for the Standard-Names ustrunc and sstrunc, include both the scalar and vector integer modes. gcc/ChangeLog: * doc/md.texi: Add Standard-Names ustrunc and sstrunc. Signed-off-by: Pan Li --- gcc/doc/md.texi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 7f4335e0aac..f116dede906 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -5543,6 +5543,18 @@ means of constraints requiring operands 1 and 0 to be the same location. @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3} Similar, for other arithmetic operations. +@cindex @code{ustrunc@var{m}@var{n}2} instruction pattern +@item @samp{ustrunc@var{m}@var{n}2} +Truncate the operand 1, and storing the result in operand 0. There will +be saturation during the trunction. The result will be saturated to the +maximal value of operand 0 type if there is overflow when truncation. The +operand 1 must have mode @var{n}, and the operand 0 must have mode @var{m}. +Both the scalar and vector integer modes are allowed. + +@cindex @code{sstrunc@var{m}@var{n}2} instruction pattern +@item @samp{sstrunc@var{m}@var{n}2} +Similar but for signed. + @cindex @code{andc@var{m}3} instruction pattern @item @samp{andc@var{m}3} Like @code{and@var{m}3}, but it uses bitwise-complement of operand 2