diff mbox series

[COMMITTED] CRIS: Adjust gcc.dg/tree-ssa/loop-1.c

Message ID 20240715030643.44A7020447@pchp3.se.axis.com
State New
Headers show
Series [COMMITTED] CRIS: Adjust gcc.dg/tree-ssa/loop-1.c | expand

Commit Message

Hans-Peter Nilsson July 15, 2024, 3:06 a.m. UTC 
Committed.
-- >8 --
With r15-1619-g3b9b8d6cfdf593, there's a XPASS and a FAIL
for this test-case for cris-elf.  Looking at the generated
code, _foo is indeed no longer saved in a register for CRIS.
While that looks like a regression, coremark results are the
same around this revision, so simply adjust the test-case:
remove the target-specific exceptions for cris-*-*.

	* gcc.dg/tree-ssa/loop-1.c: Remove target-specific test
	and xfail to adjust for recent changes in register allocation.
---
 gcc/testsuite/gcc.dg/tree-ssa/loop-1.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

Comments

Hans-Peter Nilsson July 15, 2024, 3:30 a.m. UTC | #1 
> From: Hans-Peter Nilsson <hp@axis.com>
> Date: Mon, 15 Jul 2024 05:06:43 +0200

> With r15-1619-g3b9b8d6cfdf593, there's a XPASS and a FAIL
> for this test-case for cris-elf.  Looking at the generated
> code, _foo is indeed no longer saved in a register for CRIS.
> While that looks like a regression, coremark results are the
> same around this revision, so simply adjust the test-case:
> remove the target-specific exceptions for cris-*-*.

Oh my...  That "sameness" was due to fumblefingers on my
part.  Sorry about that.  There is indeed a performance
regression at "-O2 -march=v10" for cris-elf for coremark.
Not a big one; going from 5179918 to 5181696 cycles gets me
0.034%, but still.  Maybe there are other targets affected
negatively by r15-1619-g3b9b8d6cfdf593, so I opened PR115932
to keep track.

brgds, H-P
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-1.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-1.c
index a531b7584a64..a8f2c3bbfdb4 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/loop-1.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-1.c
@@ -43,16 +43,15 @@  int xxx(void)
 /* The SH targets always use separate instructions to load the address
    and to do the actual call - bsr is only generated by link time
    relaxation.  */
-/* CRIS and MSP430 keep the address in a register.  */
+/* MSP430 keeps the address in a register.  */
 /* m68k sometimes puts the address in a register, depending on CPU and PIC.  */
 
-/* { dg-final { scan-assembler-times "foo" 5 { xfail hppa*-*-* ia64*-*-* sh*-*-* cris-*-* fido-*-* m68k-*-* i?86-*-mingw* i?86-*-cygwin* x86_64-*-mingw* visium-*-* nvptx*-*-* pdp11*-*-* msp430-*-* amdgcn*-*-* } } } */
+/* { dg-final { scan-assembler-times "foo" 5 { xfail hppa*-*-* ia64*-*-* sh*-*-* fido-*-* m68k-*-* i?86-*-mingw* i?86-*-cygwin* x86_64-*-mingw* visium-*-* nvptx*-*-* pdp11*-*-* msp430-*-* amdgcn*-*-* } } } */
 /* { dg-final { scan-assembler-times "foo,%r" 5 { target hppa*-*-* } } } */
 /* { dg-final { scan-assembler-times "= foo"  5 { target ia64*-*-* } } } */
 /* { dg-final { scan-assembler-times "call\[ \t\]*_foo" 5 { target i?86-*-mingw* i?86-*-cygwin* } } } */
 /* { dg-final { scan-assembler-times "call\[ \t\]*foo" 5 { target x86_64-*-mingw* } } } */
 /* { dg-final { scan-assembler-times "jsr|bsrf|blink\ttr?,r18"  5 { target sh*-*-* } } } */
-/* { dg-final { scan-assembler-times "Jsr \\\$r" 5 { target cris-*-* } } } */
 /* { dg-final { scan-assembler-times "\[jb\]sr" 5 { target fido-*-* m68k-*-* pdp11-*-* } } } */
 /* { dg-final { scan-assembler-times "bra *tr,r\[1-9\]*,r21" 5 { target visium-*-* } } } */
 /* { dg-final { scan-assembler-times "(?n)\[ \t\]call\[ \t\].*\[ \t\]foo," 5 { target nvptx*-*-* } } } */