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Thu, 11 Jul 2024 14:43:22 -0700 (PDT) Received: from localhost.localdomain ([139.178.84.207]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-5c7b606db30sm540950eaf.8.2024.07.11.14.43.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jul 2024 14:43:21 -0700 (PDT) From: Christophe Lyon To: gcc-patches@gcc.gnu.org, richard.earnshaw@arm.com, ramanara@nvidia.com Cc: Christophe Lyon Subject: [PATCH 04/15] arm: [MVE intrinsics] factorize vcvtq Date: Thu, 11 Jul 2024 21:42:54 +0000 Message-Id: <20240711214305.3193022-4-christophe.lyon@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240711214305.3193022-1-christophe.lyon@linaro.org> References: <20240711214305.3193022-1-christophe.lyon@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Factorize vcvtq so that they use the parameterized names. 2024-07-11 Christophe Lyon gcc/ * config/arm/iterators.md (mve_insn): Add VCVTQ_FROM_F_S, VCVTQ_FROM_F_U, VCVTQ_M_FROM_F_S, VCVTQ_M_FROM_F_U, VCVTQ_M_N_FROM_F_S, VCVTQ_M_N_FROM_F_U, VCVTQ_M_N_TO_F_S, VCVTQ_M_N_TO_F_U, VCVTQ_M_TO_F_S, VCVTQ_M_TO_F_U, VCVTQ_N_FROM_F_S, VCVTQ_N_FROM_F_U, VCVTQ_N_TO_F_S, VCVTQ_N_TO_F_U, VCVTQ_TO_F_S, VCVTQ_TO_F_U. * config/arm/mve.md (mve_vcvtq_to_f_): Rename into @mve_q_to_f_. (mve_vcvtq_from_f_): Rename into @mve_q_from_f_. (mve_vcvtq_n_to_f_): Rename into @mve_q_n_to_f_. (mve_vcvtq_n_from_f_): Rename into @mve_q_n_from_f_. (mve_vcvtq_m_to_f_): Rename into @mve_q_m_to_f_. (mve_vcvtq_m_n_from_f_): Rename into @mve_q_m_n_from_f_. (mve_vcvtq_m_from_f_): Rename into @mve_q_m_from_f_. (mve_vcvtq_m_n_to_f_): Rename into @mve_q_m_n_to_f_. --- gcc/config/arm/iterators.md | 8 +++++++ gcc/config/arm/mve.md | 48 ++++++++++++++++++------------------- 2 files changed, 32 insertions(+), 24 deletions(-) diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index b9ff01cb104..bf800625fac 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -964,6 +964,14 @@ (define_int_attr mve_insn [ (VCMLAQ_M_F "vcmla") (VCMLAQ_ROT90_M_F "vcmla") (VCMLAQ_ROT180_M_F "vcmla") (VCMLAQ_ROT270_M_F "vcmla") (VCMULQ_M_F "vcmul") (VCMULQ_ROT90_M_F "vcmul") (VCMULQ_ROT180_M_F "vcmul") (VCMULQ_ROT270_M_F "vcmul") (VCREATEQ_S "vcreate") (VCREATEQ_U "vcreate") (VCREATEQ_F "vcreate") + (VCVTQ_FROM_F_S "vcvt") (VCVTQ_FROM_F_U "vcvt") + (VCVTQ_M_FROM_F_S "vcvt") (VCVTQ_M_FROM_F_U "vcvt") + (VCVTQ_M_N_FROM_F_S "vcvt") (VCVTQ_M_N_FROM_F_U "vcvt") + (VCVTQ_M_N_TO_F_S "vcvt") (VCVTQ_M_N_TO_F_U "vcvt") + (VCVTQ_M_TO_F_S "vcvt") (VCVTQ_M_TO_F_U "vcvt") + (VCVTQ_N_FROM_F_S "vcvt") (VCVTQ_N_FROM_F_U "vcvt") + (VCVTQ_N_TO_F_S "vcvt") (VCVTQ_N_TO_F_U "vcvt") + (VCVTQ_TO_F_S "vcvt") (VCVTQ_TO_F_U "vcvt") (VDUPQ_M_N_S "vdup") (VDUPQ_M_N_U "vdup") (VDUPQ_M_N_F "vdup") (VDUPQ_N_S "vdup") (VDUPQ_N_U "vdup") (VDUPQ_N_F "vdup") (VEORQ_M_S "veor") (VEORQ_M_U "veor") (VEORQ_M_F "veor") diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 4b4d6298ffb..b339d0ccdf6 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -250,15 +250,15 @@ (define_insn "mve_vcvtbq_f32_f16v4sf" ;; ;; [vcvtq_to_f_s, vcvtq_to_f_u]) ;; -(define_insn "mve_vcvtq_to_f_" +(define_insn "@mve_q_to_f_" [ (set (match_operand:MVE_0 0 "s_register_operand" "=w") (unspec:MVE_0 [(match_operand: 1 "s_register_operand" "w")] VCVTQ_TO_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vcvt.f%#.%#\t%q0, %q1" - [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtq_to_f_")) + ".f%#.%#\t%q0, %q1" + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_to_f_")) (set_attr "type" "mve_move") ]) @@ -280,15 +280,15 @@ (define_insn "@mve_q_" ;; ;; [vcvtq_from_f_s, vcvtq_from_f_u]) ;; -(define_insn "mve_vcvtq_from_f_" +(define_insn "@mve_q_from_f_" [ (set (match_operand:MVE_5 0 "s_register_operand" "=w") (unspec:MVE_5 [(match_operand: 1 "s_register_operand" "w")] VCVTQ_FROM_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vcvt.%#.f%#\t%q0, %q1" - [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtq_from_f_")) + ".%#.f%#\t%q0, %q1" + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_from_f_")) (set_attr "type" "mve_move") ]) @@ -583,7 +583,7 @@ (define_insn "@mve_q_n_f" ;; ;; [vcvtq_n_to_f_s, vcvtq_n_to_f_u]) ;; -(define_insn "mve_vcvtq_n_to_f_" +(define_insn "@mve_q_n_to_f_" [ (set (match_operand:MVE_0 0 "s_register_operand" "=w") (unspec:MVE_0 [(match_operand: 1 "s_register_operand" "w") @@ -591,8 +591,8 @@ (define_insn "mve_vcvtq_n_to_f_" VCVTQ_N_TO_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vcvt.f.\t%q0, %q1, %2" - [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtq_n_to_f_")) + ".f.\t%q0, %q1, %2" + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_to_f_")) (set_attr "type" "mve_move") ]) @@ -681,7 +681,7 @@ (define_insn "mve_vshrq_n_u_imm" ;; ;; [vcvtq_n_from_f_s, vcvtq_n_from_f_u]) ;; -(define_insn "mve_vcvtq_n_from_f_" +(define_insn "@mve_q_n_from_f_" [ (set (match_operand:MVE_5 0 "s_register_operand" "=w") (unspec:MVE_5 [(match_operand: 1 "s_register_operand" "w") @@ -689,8 +689,8 @@ (define_insn "mve_vcvtq_n_from_f_" VCVTQ_N_FROM_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vcvt..f\t%q0, %q1, %2" - [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtq_n_from_f_")) + "..f\t%q0, %q1, %2" + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_from_f_")) (set_attr "type" "mve_move") ]) @@ -1674,7 +1674,7 @@ (define_insn "mve_vcvtaq_m_" ;; ;; [vcvtq_m_to_f_s, vcvtq_m_to_f_u]) ;; -(define_insn "mve_vcvtq_m_to_f_" +(define_insn "@mve_q_m_to_f_" [ (set (match_operand:MVE_0 0 "s_register_operand" "=w") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") @@ -1683,8 +1683,8 @@ (define_insn "mve_vcvtq_m_to_f_" VCVTQ_M_TO_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcvtt.f%#.%#\t%q0, %q2" - [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtq_to_f_")) + "vpst\;t.f%#.%#\t%q0, %q2" + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_to_f_")) (set_attr "type" "mve_move") (set_attr "length""8")]) @@ -2653,7 +2653,7 @@ (define_insn "mve_vcvtnq_m_" ;; ;; [vcvtq_m_n_from_f_s, vcvtq_m_n_from_f_u]) ;; -(define_insn "mve_vcvtq_m_n_from_f_" +(define_insn "@mve_q_m_n_from_f_" [ (set (match_operand:MVE_5 0 "s_register_operand" "=w") (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") @@ -2663,8 +2663,8 @@ (define_insn "mve_vcvtq_m_n_from_f_" VCVTQ_M_N_FROM_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcvtt.%#.f%#\t%q0, %q2, %3" - [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtq_n_from_f_")) + "vpst\;t.%#.f%#\t%q0, %q2, %3" + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_from_f_")) (set_attr "type" "mve_move") (set_attr "length""8")]) @@ -2688,7 +2688,7 @@ (define_insn "@mve_q_m_" ;; ;; [vcvtq_m_from_f_u, vcvtq_m_from_f_s]) ;; -(define_insn "mve_vcvtq_m_from_f_" +(define_insn "@mve_q_m_from_f_" [ (set (match_operand:MVE_5 0 "s_register_operand" "=w") (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") @@ -2697,8 +2697,8 @@ (define_insn "mve_vcvtq_m_from_f_" VCVTQ_M_FROM_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcvtt.%#.f%#\t%q0, %q2" - [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtq_from_f_")) + "vpst\;t.%#.f%#\t%q0, %q2" + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_from_f_")) (set_attr "type" "mve_move") (set_attr "length""8")]) @@ -2759,7 +2759,7 @@ (define_insn "@mve_q_m_n_" ;; ;; [vcvtq_m_n_to_f_u, vcvtq_m_n_to_f_s]) ;; -(define_insn "mve_vcvtq_m_n_to_f_" +(define_insn "@mve_q_m_n_to_f_" [ (set (match_operand:MVE_0 0 "s_register_operand" "=w") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") @@ -2769,8 +2769,8 @@ (define_insn "mve_vcvtq_m_n_to_f_" VCVTQ_M_N_TO_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcvtt.f%#.%#\t%q0, %q2, %3" - [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtq_n_to_f_")) + "vpst\;t.f%#.%#\t%q0, %q2, %3" + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_to_f_")) (set_attr "type" "mve_move") (set_attr "length""8")])