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X-CSE-ConnectionGUID: UNmECZeURE6j3Zs0HVHVYA== X-CSE-MsgGUID: LWqizMfbTCWGsLrZcKOzXA== X-IronPort-AV: E=McAfee;i="6700,10204,11128"; a="18051002" X-IronPort-AV: E=Sophos;i="6.09,197,1716274800"; d="scan'208";a="18051002" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jul 2024 02:27:58 -0700 X-CSE-ConnectionGUID: 2UayJfD0RCOD/zXiVa2lTQ== X-CSE-MsgGUID: uMuEBs7FQSCiuAD23kMwAQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,197,1716274800"; d="scan'208";a="47920577" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by fmviesa006.fm.intel.com with ESMTP; 10 Jul 2024 02:27:55 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id D1F13100570C; Wed, 10 Jul 2024 17:27:54 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, richard.guenther@gmail.com, tamar.christina@arm.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, hongtao.liu@intel.com, Pan Li Subject: [PATCH v1] Vect: Promote unsigned .SAT_ADD constant operand for vectorizable_call Date: Wed, 10 Jul 2024 17:27:53 +0800 Message-Id: <20240710092753.3810342-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li The .SAT_ADD has 2 operand and one of the operand may be INTEGER_CST. For example _1 = .SAT_ADD (_2, 9) comes from below sample code. Form 3: #define DEF_VEC_SAT_U_ADD_IMM_FMT_3(T, IMM) \ T __attribute__((noinline)) \ vec_sat_u_add_imm##IMM##_##T##_fmt_3 (T *out, T *in, unsigned limit) \ { \ unsigned i; \ T ret; \ for (i = 0; i < limit; i++) \ { \ out[i] = __builtin_add_overflow (in[i], IMM, &ret) ? -1 : ret; \ } \ } DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint64_t, 9) It will failure to vectorize as the vectorizable_call will check the operands is type_compatiable but the imm will be treated as unsigned SImode from the perspective of tree. Aka uint64_t _1; uint64_t _2; _1 = .SAT_ADD (_2, 9); The _1 and _2 are unsigned DImode, which is different to imm 9 unsigned SImode, and then result in vectorizable_call fails. This patch would like to promote the imm operand to the operand type mode of _2 if and only if there is no precision/data loss. Aka convert the imm 9 to the DImode for above example. The below test suites are passed for this patch: 1. The rv64gcv fully regression tests. 2. The rv64gcv build with glibc. 3. The x86 bootstrap tests. 4. The x86 fully regression tests. gcc/ChangeLog: * tree-vect-patterns.cc (vect_recog_promote_cst_to_unsigned): Add new func impl to promote the imm tree to target type. (vect_recog_sat_add_pattern): Peform the type promotion before generate .SAT_ADD call. Signed-off-by: Pan Li --- gcc/tree-vect-patterns.cc | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/gcc/tree-vect-patterns.cc b/gcc/tree-vect-patterns.cc index 86e893a1c43..e1013222b12 100644 --- a/gcc/tree-vect-patterns.cc +++ b/gcc/tree-vect-patterns.cc @@ -4527,6 +4527,20 @@ vect_recog_build_binary_gimple_stmt (vec_info *vinfo, stmt_vec_info stmt_info, return NULL; } +static void +vect_recog_promote_cst_to_unsigned (tree *op, tree type) +{ + if (TREE_CODE (*op) != INTEGER_CST || !TYPE_UNSIGNED (type)) + return; + + unsigned precision = TYPE_PRECISION (type); + wide_int type_max = wi::mask (precision, false, precision); + wide_int op_cst_val = wi::to_wide (*op, precision); + + if (wi::leu_p (op_cst_val, type_max)) + *op = wide_int_to_tree (type, op_cst_val); +} + /* * Try to detect saturation add pattern (SAT_ADD), aka below gimple: * _7 = _4 + _6; @@ -4553,6 +4567,9 @@ vect_recog_sat_add_pattern (vec_info *vinfo, stmt_vec_info stmt_vinfo, if (gimple_unsigned_integer_sat_add (lhs, ops, NULL)) { + vect_recog_promote_cst_to_unsigned (&ops[0], TREE_TYPE (ops[1])); + vect_recog_promote_cst_to_unsigned (&ops[1], TREE_TYPE (ops[0])); + gimple *stmt = vect_recog_build_binary_gimple_stmt (vinfo, stmt_vinfo, IFN_SAT_ADD, type_out, lhs, ops[0], ops[1]);