| Message ID | 20240709024638.19717-1-gaofei@eswincomputing.com |
|---|---|
| State | New |
| Headers | show |
| Series | None | expand |
LGTM, thanks :) On Tue, Jul 9, 2024 at 10:47 AM Fei Gao <gaofei@eswincomputing.com> wrote: > According to Zc-1.0.4-3.pdf from > > https://github.com/riscvarchive/riscv-code-size-reduction/releases/tag/v1.0.4-3 > The rule is that: > 1. C always implies Zca > 2. C+F implies Zcf (RV32 only) > 3. C+D implies Zcd > > gcc/ChangeLog: > > * common/config/riscv/riscv-common.cc: > c implies zca, and conditionally zcf & zcd. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/attribute-15.c: adapt TC. > * gcc.target/riscv/attribute-18.c: likewise. > * gcc.target/riscv/pr110696.c: likewise. > * gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c: likewise. > * gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c: likewise. > * gcc.target/riscv/rvv/base/pr114352-1.c: likewise. > * gcc.target/riscv/rvv/base/pr114352-3.c: likewise. > * gcc.target/riscv/arch-39.c: New test. > * gcc.target/riscv/arch-40.c: New test. > > > Signed-off-by: Fei Gao <gaofei@eswincomputing.com> > --- > gcc/common/config/riscv/riscv-common.cc | 12 ++++++++++++ > gcc/testsuite/gcc.target/riscv/arch-39.c | 7 +++++++ > gcc/testsuite/gcc.target/riscv/arch-40.c | 7 +++++++ > gcc/testsuite/gcc.target/riscv/attribute-15.c | 2 +- > gcc/testsuite/gcc.target/riscv/attribute-18.c | 2 +- > gcc/testsuite/gcc.target/riscv/pr110696.c | 2 +- > .../riscv/rvv/base/abi-callee-saved-1-zcmp.c | 2 +- > .../riscv/rvv/base/abi-callee-saved-2-zcmp.c | 2 +- > gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c | 4 ++-- > gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c | 8 ++++---- > 10 files changed, 37 insertions(+), 11 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/arch-39.c > create mode 100644 gcc/testsuite/gcc.target/riscv/arch-40.c > > diff --git a/gcc/common/config/riscv/riscv-common.cc > b/gcc/common/config/riscv/riscv-common.cc > index cad3551feb6..a02f1fe19a0 100644 > --- a/gcc/common/config/riscv/riscv-common.cc > +++ b/gcc/common/config/riscv/riscv-common.cc > @@ -82,6 +82,18 @@ static const riscv_implied_info_t riscv_implied_info[] = > {"a", "zaamo"}, > {"a", "zalrsc"}, > > + {"c", "zca"}, > + {"c", "zcf", > + [] (const riscv_subset_list *subset_list) -> bool > + { > + return subset_list->xlen () == 32 && subset_list->lookup ("f"); > + }}, > + {"c", "zcd", > + [] (const riscv_subset_list *subset_list) -> bool > + { > + return subset_list->lookup ("d"); > + }}, > + > {"zdinx", "zfinx"}, > {"zfinx", "zicsr"}, > {"zdinx", "zicsr"}, > diff --git a/gcc/testsuite/gcc.target/riscv/arch-39.c > b/gcc/testsuite/gcc.target/riscv/arch-39.c > new file mode 100644 > index 00000000000..beeb81e44c5 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/arch-39.c > @@ -0,0 +1,7 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64idc_zcmt -mabi=lp64d" } */ > +int > +foo () > +{} > + > +/* { dg-error "zcd conflicts with zcmt" "" { target *-*-* } 0 } */ > diff --git a/gcc/testsuite/gcc.target/riscv/arch-40.c > b/gcc/testsuite/gcc.target/riscv/arch-40.c > new file mode 100644 > index 00000000000..eaefaf1d0d7 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/arch-40.c > @@ -0,0 +1,7 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64idc_zcmp -mabi=lp64d" } */ > +int > +foo () > +{} > + > +/* { dg-error "zcd conflicts with zcmp" "" { target *-*-* } 0 } */ > diff --git a/gcc/testsuite/gcc.target/riscv/attribute-15.c > b/gcc/testsuite/gcc.target/riscv/attribute-15.c > index a2e394b6489..ac6caaecd4f 100644 > --- a/gcc/testsuite/gcc.target/riscv/attribute-15.c > +++ b/gcc/testsuite/gcc.target/riscv/attribute-15.c > @@ -3,4 +3,4 @@ > int foo() > { > } > -/* { dg-final { scan-assembler ".attribute arch, > \"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0\"" } } */ > +/* { dg-final { scan-assembler ".attribute arch, > \"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0\"" > } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/attribute-18.c > b/gcc/testsuite/gcc.target/riscv/attribute-18.c > index eefd602103d..9f7199f331a 100644 > --- a/gcc/testsuite/gcc.target/riscv/attribute-18.c > +++ b/gcc/testsuite/gcc.target/riscv/attribute-18.c > @@ -1,4 +1,4 @@ > /* { dg-do compile } */ > /* { dg-options "-mriscv-attribute -march=rv64imafdc -mabi=lp64d > -misa-spec=2.2" } */ > int foo() {} > -/* { dg-final { scan-assembler ".attribute arch, > \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0\"" } } */ > +/* { dg-final { scan-assembler ".attribute arch, > \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0\"" } } > */ > diff --git a/gcc/testsuite/gcc.target/riscv/pr110696.c > b/gcc/testsuite/gcc.target/riscv/pr110696.c > index 08682a047e0..8aa6cd07f4f 100644 > --- a/gcc/testsuite/gcc.target/riscv/pr110696.c > +++ b/gcc/testsuite/gcc.target/riscv/pr110696.c > @@ -4,4 +4,4 @@ int foo() > { > } > > -/* { dg-final { scan-assembler ".attribute arch, > \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" > } } */ > +/* { dg-final { scan-assembler ".attribute arch, > \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1_zca1p0_zcd1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" > } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c > b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c > index dedcef9b353..b6b708f1a58 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-options "-O1 -march=rv64gcv_zfh_zca_zcmp -mabi=lp64d > -fno-shrink-wrap-separate" } */ > +/* { dg-options "-O1 -march=rv64gv_zfh_zca_zcmp -mabi=lp64d > -fno-shrink-wrap-separate" } */ > /* { dg-final { check-function-bodies "**" "" } } */ > > #include <riscv_vector.h> > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c > b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c > index 14fb2c400a4..5f8f96f86a9 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-options "-O1 -march=rv64gcv_zfh_zca_zcmp -mabi=lp64d > -fno-shrink-wrap-separate" } */ > +/* { dg-options "-O1 -march=rv64gv_zfh_zca_zcmp -mabi=lp64d > -fno-shrink-wrap-separate" } */ > /* { dg-final { check-function-bodies "**" "" } } */ > > #include <riscv_vector.h> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c > b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c > index faeb406498d..aa9c7fa18d5 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c > @@ -54,5 +54,5 @@ test_3 (int *a, int *b, int *out, unsigned count) > out[i] = a[i] + b[i]; > } > > -/* { dg-final { scan-assembler ".attribute arch, > \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" > } } */ > -/* { dg-final { scan-assembler ".option arch, > rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" > } } */ > +/* { dg-final { scan-assembler ".attribute arch, > \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1_zca1p0_zcd1p0\"" > } } */ > +/* { dg-final { scan-assembler ".option arch, > rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1_zca1p0_zcd1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" > } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c > b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c > index 38815ef5bd0..dff9198ecaa 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c > @@ -107,7 +107,7 @@ test_6 (_Float16 *a, _Float16 *b, _Float16 *out, > unsigned count) > out[i] = a[i] + b[i]; > } > > -/* { dg-final { scan-assembler ".attribute arch, > \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" > } } */ > -/* { dg-final { scan-assembler ".option arch, > rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" > } } */ > -/* { dg-final { scan-assembler ".option arch, > rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zbb1p0" > } } */ > -/* { dg-final { scan-assembler ".option arch, > rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zfh1p0_zfhmin1p0" > } } */ > +/* { dg-final { scan-assembler ".attribute arch, > \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1_zca1p0_zcd1p0\"" > } } */ > +/* { dg-final { scan-assembler ".option arch, > rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1_zca1p0_zcd1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" > } } */ > +/* { dg-final { scan-assembler ".option arch, > rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1_zca1p0_zcd1p0_zbb1p0" > } } */ > +/* { dg-final { scan-assembler ".option arch, > rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zfh1p0_zfhmin1p0_zaamo1p0_zalrsc1_zca1p0_zcd1p0" > } } */ > -- > 2.17.1 > >
On 2024-07-09 11:10 Kito Cheng <kito.cheng@gmail.com> wrote: > >LGTM, thanks :) > This patch still fails to apply in patchwork. Just realized it conflicts with a recent merge. So I rebased and resent a new patch. Sorry to spam. BR Fei >On Tue, Jul 9, 2024 at 10:47 AM Fei Gao <gaofei@eswincomputing.com> wrote: > >> According to Zc-1.0.4-3.pdf from >> >> https://github.com/riscvarchive/riscv-code-size-reduction/releases/tag/v1.0.4-3 >> The rule is that: >> 1. C always implies Zca >> 2. C+F implies Zcf (RV32 only) >> 3. C+D implies Zcd >> >> gcc/ChangeLog: >> >> * common/config/riscv/riscv-common.cc: >> c implies zca, and conditionally zcf & zcd. >> >> gcc/testsuite/ChangeLog: >> >> * gcc.target/riscv/attribute-15.c: adapt TC. >> * gcc.target/riscv/attribute-18.c: likewise. >> * gcc.target/riscv/pr110696.c: likewise. >> * gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c: likewise. >> * gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c: likewise. >> * gcc.target/riscv/rvv/base/pr114352-1.c: likewise. >> * gcc.target/riscv/rvv/base/pr114352-3.c: likewise. >> * gcc.target/riscv/arch-39.c: New test. >> * gcc.target/riscv/arch-40.c: New test. >> >> >> Signed-off-by: Fei Gao <gaofei@eswincomputing.com> >> --- >> gcc/common/config/riscv/riscv-common.cc | 12 ++++++++++++ >> gcc/testsuite/gcc.target/riscv/arch-39.c | 7 +++++++ >> gcc/testsuite/gcc.target/riscv/arch-40.c | 7 +++++++ >> gcc/testsuite/gcc.target/riscv/attribute-15.c | 2 +- >> gcc/testsuite/gcc.target/riscv/attribute-18.c | 2 +- >> gcc/testsuite/gcc.target/riscv/pr110696.c | 2 +- >> .../riscv/rvv/base/abi-callee-saved-1-zcmp.c | 2 +- >> .../riscv/rvv/base/abi-callee-saved-2-zcmp.c | 2 +- >> gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c | 4 ++-- >> gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c | 8 ++++---- >> 10 files changed, 37 insertions(+), 11 deletions(-) >> create mode 100644 gcc/testsuite/gcc.target/riscv/arch-39.c >> create mode 100644 gcc/testsuite/gcc.target/riscv/arch-40.c >> >> diff --git a/gcc/common/config/riscv/riscv-common.cc >> b/gcc/common/config/riscv/riscv-common.cc >> index cad3551feb6..a02f1fe19a0 100644 >> --- a/gcc/common/config/riscv/riscv-common.cc >> +++ b/gcc/common/config/riscv/riscv-common.cc >> @@ -82,6 +82,18 @@ static const riscv_implied_info_t riscv_implied_info[] = >> {"a", "zaamo"}, >> {"a", "zalrsc"}, >> >> + {"c", "zca"}, >> + {"c", "zcf", >> + [] (const riscv_subset_list *subset_list) -> bool >> + { >> + return subset_list->xlen () == 32 && subset_list->lookup ("f"); >> + }}, >> + {"c", "zcd", >> + [] (const riscv_subset_list *subset_list) -> bool >> + { >> + return subset_list->lookup ("d"); >> + }}, >> + >> {"zdinx", "zfinx"}, >> {"zfinx", "zicsr"}, >> {"zdinx", "zicsr"}, >> diff --git a/gcc/testsuite/gcc.target/riscv/arch-39.c >> b/gcc/testsuite/gcc.target/riscv/arch-39.c >> new file mode 100644 >> index 00000000000..beeb81e44c5 >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/riscv/arch-39.c >> @@ -0,0 +1,7 @@ >> +/* { dg-do compile } */ >> +/* { dg-options "-march=rv64idc_zcmt -mabi=lp64d" } */ >> +int >> +foo () >> +{} >> + >> +/* { dg-error "zcd conflicts with zcmt" "" { target *-*-* } 0 } */ >> diff --git a/gcc/testsuite/gcc.target/riscv/arch-40.c >> b/gcc/testsuite/gcc.target/riscv/arch-40.c >> new file mode 100644 >> index 00000000000..eaefaf1d0d7 >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/riscv/arch-40.c >> @@ -0,0 +1,7 @@ >> +/* { dg-do compile } */ >> +/* { dg-options "-march=rv64idc_zcmp -mabi=lp64d" } */ >> +int >> +foo () >> +{} >> + >> +/* { dg-error "zcd conflicts with zcmp" "" { target *-*-* } 0 } */ >> diff --git a/gcc/testsuite/gcc.target/riscv/attribute-15.c >> b/gcc/testsuite/gcc.target/riscv/attribute-15.c >> index a2e394b6489..ac6caaecd4f 100644 >> --- a/gcc/testsuite/gcc.target/riscv/attribute-15.c >> +++ b/gcc/testsuite/gcc.target/riscv/attribute-15.c >> @@ -3,4 +3,4 @@ >> int foo() >> { >> } >> -/* { dg-final { scan-assembler ".attribute arch, >> \"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0\"" } } */ >> +/* { dg-final { scan-assembler ".attribute arch, >> \"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0\"" >> } } */ >> diff --git a/gcc/testsuite/gcc.target/riscv/attribute-18.c >> b/gcc/testsuite/gcc.target/riscv/attribute-18.c >> index eefd602103d..9f7199f331a 100644 >> --- a/gcc/testsuite/gcc.target/riscv/attribute-18.c >> +++ b/gcc/testsuite/gcc.target/riscv/attribute-18.c >> @@ -1,4 +1,4 @@ >> /* { dg-do compile } */ >> /* { dg-options "-mriscv-attribute -march=rv64imafdc -mabi=lp64d >> -misa-spec=2.2" } */ >> int foo() {} >> -/* { dg-final { scan-assembler ".attribute arch, >> \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0\"" } } */ >> +/* { dg-final { scan-assembler ".attribute arch, >> \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0\"" } } >> */ >> diff --git a/gcc/testsuite/gcc.target/riscv/pr110696.c >> b/gcc/testsuite/gcc.target/riscv/pr110696.c >> index 08682a047e0..8aa6cd07f4f 100644 >> --- a/gcc/testsuite/gcc.target/riscv/pr110696.c >> +++ b/gcc/testsuite/gcc.target/riscv/pr110696.c >> @@ -4,4 +4,4 @@ int foo() >> { >> } >> >> -/* { dg-final { scan-assembler ".attribute arch, >> \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" >> } } */ >> +/* { dg-final { scan-assembler ".attribute arch, >> \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1_zca1p0_zcd1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" >> } } */ >> diff --git >> a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c >> b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c >> index dedcef9b353..b6b708f1a58 100644 >> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c >> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c >> @@ -1,5 +1,5 @@ >> /* { dg-do compile } */ >> -/* { dg-options "-O1 -march=rv64gcv_zfh_zca_zcmp -mabi=lp64d >> -fno-shrink-wrap-separate" } */ >> +/* { dg-options "-O1 -march=rv64gv_zfh_zca_zcmp -mabi=lp64d >> -fno-shrink-wrap-separate" } */ >> /* { dg-final { check-function-bodies "**" "" } } */ >> >> #include <riscv_vector.h> >> diff --git >> a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c >> b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c >> index 14fb2c400a4..5f8f96f86a9 100644 >> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c >> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c >> @@ -1,5 +1,5 @@ >> /* { dg-do compile } */ >> -/* { dg-options "-O1 -march=rv64gcv_zfh_zca_zcmp -mabi=lp64d >> -fno-shrink-wrap-separate" } */ >> +/* { dg-options "-O1 -march=rv64gv_zfh_zca_zcmp -mabi=lp64d >> -fno-shrink-wrap-separate" } */ >> /* { dg-final { check-function-bodies "**" "" } } */ >> >> #include <riscv_vector.h> >> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c >> b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c >> index faeb406498d..aa9c7fa18d5 100644 >> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c >> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c >> @@ -54,5 +54,5 @@ test_3 (int *a, int *b, int *out, unsigned count) >> out[i] = a[i] + b[i]; >> } >> >> -/* { dg-final { scan-assembler ".attribute arch, >> \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" >> } } */ >> -/* { dg-final { scan-assembler ".option arch, >> rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" >> } } */ >> +/* { dg-final { scan-assembler ".attribute arch, >> \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1_zca1p0_zcd1p0\"" >> } } */ >> +/* { dg-final { scan-assembler ".option arch, >> rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1_zca1p0_zcd1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" >> } } */ >> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c >> b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c >> index 38815ef5bd0..dff9198ecaa 100644 >> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c >> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c >> @@ -107,7 +107,7 @@ test_6 (_Float16 *a, _Float16 *b, _Float16 *out, >> unsigned count) >> out[i] = a[i] + b[i]; >> } >> >> -/* { dg-final { scan-assembler ".attribute arch, >> \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" >> } } */ >> -/* { dg-final { scan-assembler ".option arch, >> rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" >> } } */ >> -/* { dg-final { scan-assembler ".option arch, >> rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zbb1p0" >> } } */ >> -/* { dg-final { scan-assembler ".option arch, >> rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zfh1p0_zfhmin1p0" >> } } */ >> +/* { dg-final { scan-assembler ".attribute arch, >> \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1_zca1p0_zcd1p0\"" >> } } */ >> +/* { dg-final { scan-assembler ".option arch, >> rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1_zca1p0_zcd1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" >> } } */ >> +/* { dg-final { scan-assembler ".option arch, >> rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1_zca1p0_zcd1p0_zbb1p0" >> } } */ >> +/* { dg-final { scan-assembler ".option arch, >> rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zfh1p0_zfhmin1p0_zaamo1p0_zalrsc1_zca1p0_zcd1p0" >> } } */ >> -- >> 2.17.1 >> >>
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index cad3551feb6..a02f1fe19a0 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -82,6 +82,18 @@ static const riscv_implied_info_t riscv_implied_info[] = {"a", "zaamo"}, {"a", "zalrsc"}, + {"c", "zca"}, + {"c", "zcf", + [] (const riscv_subset_list *subset_list) -> bool + { + return subset_list->xlen () == 32 && subset_list->lookup ("f"); + }}, + {"c", "zcd", + [] (const riscv_subset_list *subset_list) -> bool + { + return subset_list->lookup ("d"); + }}, + {"zdinx", "zfinx"}, {"zfinx", "zicsr"}, {"zdinx", "zicsr"}, diff --git a/gcc/testsuite/gcc.target/riscv/arch-39.c b/gcc/testsuite/gcc.target/riscv/arch-39.c new file mode 100644 index 00000000000..beeb81e44c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-39.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64idc_zcmt -mabi=lp64d" } */ +int +foo () +{} + +/* { dg-error "zcd conflicts with zcmt" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-40.c b/gcc/testsuite/gcc.target/riscv/arch-40.c new file mode 100644 index 00000000000..eaefaf1d0d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-40.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64idc_zcmp -mabi=lp64d" } */ +int +foo () +{} + +/* { dg-error "zcd conflicts with zcmp" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-15.c b/gcc/testsuite/gcc.target/riscv/attribute-15.c index a2e394b6489..ac6caaecd4f 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-15.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-15.c @@ -3,4 +3,4 @@ int foo() { } -/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0\"" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-18.c b/gcc/testsuite/gcc.target/riscv/attribute-18.c index eefd602103d..9f7199f331a 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-18.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-18.c @@ -1,4 +1,4 @@ /* { dg-do compile } */ /* { dg-options "-mriscv-attribute -march=rv64imafdc -mabi=lp64d -misa-spec=2.2" } */ int foo() {} -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0\"" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr110696.c b/gcc/testsuite/gcc.target/riscv/pr110696.c index 08682a047e0..8aa6cd07f4f 100644 --- a/gcc/testsuite/gcc.target/riscv/pr110696.c +++ b/gcc/testsuite/gcc.target/riscv/pr110696.c @@ -4,4 +4,4 @@ int foo() { } -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1_zca1p0_zcd1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c index dedcef9b353..b6b708f1a58 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O1 -march=rv64gcv_zfh_zca_zcmp -mabi=lp64d -fno-shrink-wrap-separate" } */ +/* { dg-options "-O1 -march=rv64gv_zfh_zca_zcmp -mabi=lp64d -fno-shrink-wrap-separate" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include <riscv_vector.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c index 14fb2c400a4..5f8f96f86a9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O1 -march=rv64gcv_zfh_zca_zcmp -mabi=lp64d -fno-shrink-wrap-separate" } */ +/* { dg-options "-O1 -march=rv64gv_zfh_zca_zcmp -mabi=lp64d -fno-shrink-wrap-separate" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include <riscv_vector.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c index faeb406498d..aa9c7fa18d5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c @@ -54,5 +54,5 @@ test_3 (int *a, int *b, int *out, unsigned count) out[i] = a[i] + b[i]; } -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */ -/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1_zca1p0_zcd1p0\"" } } */ +/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1_zca1p0_zcd1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c index 38815ef5bd0..dff9198ecaa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c @@ -107,7 +107,7 @@ test_6 (_Float16 *a, _Float16 *b, _Float16 *out, unsigned count) out[i] = a[i] + b[i]; } -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */ -/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */ -/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zbb1p0" } } */ -/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zfh1p0_zfhmin1p0" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1_zca1p0_zcd1p0\"" } } */ +/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1_zca1p0_zcd1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */ +/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1_zca1p0_zcd1p0_zbb1p0" } } */ +/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zfh1p0_zfhmin1p0_zaamo1p0_zalrsc1_zca1p0_zcd1p0" } } */
According to Zc-1.0.4-3.pdf from https://github.com/riscvarchive/riscv-code-size-reduction/releases/tag/v1.0.4-3 The rule is that: 1. C always implies Zca 2. C+F implies Zcf (RV32 only) 3. C+D implies Zcd gcc/ChangeLog: * common/config/riscv/riscv-common.cc: c implies zca, and conditionally zcf & zcd. gcc/testsuite/ChangeLog: * gcc.target/riscv/attribute-15.c: adapt TC. * gcc.target/riscv/attribute-18.c: likewise. * gcc.target/riscv/pr110696.c: likewise. * gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c: likewise. * gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c: likewise. * gcc.target/riscv/rvv/base/pr114352-1.c: likewise. * gcc.target/riscv/rvv/base/pr114352-3.c: likewise. * gcc.target/riscv/arch-39.c: New test. * gcc.target/riscv/arch-40.c: New test. Signed-off-by: Fei Gao <gaofei@eswincomputing.com> --- gcc/common/config/riscv/riscv-common.cc | 12 ++++++++++++ gcc/testsuite/gcc.target/riscv/arch-39.c | 7 +++++++ gcc/testsuite/gcc.target/riscv/arch-40.c | 7 +++++++ gcc/testsuite/gcc.target/riscv/attribute-15.c | 2 +- gcc/testsuite/gcc.target/riscv/attribute-18.c | 2 +- gcc/testsuite/gcc.target/riscv/pr110696.c | 2 +- .../riscv/rvv/base/abi-callee-saved-1-zcmp.c | 2 +- .../riscv/rvv/base/abi-callee-saved-2-zcmp.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c | 4 ++-- gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c | 8 ++++---- 10 files changed, 37 insertions(+), 11 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/arch-39.c create mode 100644 gcc/testsuite/gcc.target/riscv/arch-40.c