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X-CSE-ConnectionGUID: JJJlDaFlSt6une2F7UFMRQ== X-CSE-MsgGUID: zpz1xztrQ2qrKc+7NnkmIg== X-IronPort-AV: E=McAfee;i="6700,10204,11119"; a="27520903" X-IronPort-AV: E=Sophos;i="6.09,175,1716274800"; d="scan'208";a="27520903" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jun 2024 18:35:47 -0700 X-CSE-ConnectionGUID: gG7CrX4tR5W4gtMCyfA64g== X-CSE-MsgGUID: EaqMIRw3TY2ZYgwq68CCTg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,175,1716274800"; d="scan'208";a="76524330" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmviesa001.fm.intel.com with ESMTP; 30 Jun 2024 18:35:44 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 07DF11007356; Mon, 1 Jul 2024 09:35:43 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v1 3/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 3 Date: Mon, 1 Jul 2024 09:35:38 +0800 Message-Id: <20240701013539.776849-3-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240701013539.776849-1-pan2.li@intel.com> References: <20240701013539.776849-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_LOTSOFHASH, KAM_NUMSUBJECT, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li This patch would like to add test cases for the unsigned scalar .SAT_ADD IMM form 3. Aka: Form 3: #define DEF_SAT_U_ADD_IMM_FMT_3(T) \ T __attribute__((noinline)) \ sat_u_add_imm_##T##_fmt_3 (T x) \ { \ T ret; \ return __builtin_add_overflow (x, 8, &ret) ? -1 : ret; \ } DEF_SAT_U_ADD_IMM_FMT_3(uint64_t) The below test is passed for this patch. * The rv64gcv regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_arith.h: Add helper test macro. * gcc.target/riscv/sat_u_add_imm-10.c: New test. * gcc.target/riscv/sat_u_add_imm-11.c: New test. * gcc.target/riscv/sat_u_add_imm-12.c: New test. * gcc.target/riscv/sat_u_add_imm-9.c: New test. * gcc.target/riscv/sat_u_add_imm-run-10.c: New test. * gcc.target/riscv/sat_u_add_imm-run-11.c: New test. * gcc.target/riscv/sat_u_add_imm-run-12.c: New test. * gcc.target/riscv/sat_u_add_imm-run-9.c: New test. Signed-off-by: Pan Li Signed-off-by: Pan Li --- gcc/testsuite/gcc.target/riscv/sat_arith.h | 11 +++++ .../gcc.target/riscv/sat_u_add_imm-10.c | 21 +++++++++ .../gcc.target/riscv/sat_u_add_imm-11.c | 18 ++++++++ .../gcc.target/riscv/sat_u_add_imm-12.c | 17 +++++++ .../gcc.target/riscv/sat_u_add_imm-9.c | 19 ++++++++ .../gcc.target/riscv/sat_u_add_imm-run-10.c | 46 +++++++++++++++++++ .../gcc.target/riscv/sat_u_add_imm-run-11.c | 46 +++++++++++++++++++ .../gcc.target/riscv/sat_u_add_imm-run-12.c | 46 +++++++++++++++++++ .../gcc.target/riscv/sat_u_add_imm-run-9.c | 46 +++++++++++++++++++ 9 files changed, 270 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-11.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-12.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-9.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-11.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-12.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-9.c diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h index d94f0fd602c..83b294db476 100644 --- a/gcc/testsuite/gcc.target/riscv/sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h @@ -74,12 +74,23 @@ sat_u_add_imm##IMM##_##T##_fmt_2 (T x) \ return (T)(x + IMM) < x ? -1 : (x + IMM); \ } +#define DEF_SAT_U_ADD_IMM_FMT_3(T, IMM) \ +T __attribute__((noinline)) \ +sat_u_add_imm##IMM##_##T##_fmt_3 (T x) \ +{ \ + T ret; \ + return __builtin_add_overflow (x, IMM, &ret) ? -1 : ret; \ +} + #define RUN_SAT_U_ADD_IMM_FMT_1(T, x, IMM, expect) \ if (sat_u_add_imm##IMM##_##T##_fmt_1(x) != expect) __builtin_abort () #define RUN_SAT_U_ADD_IMM_FMT_2(T, x, IMM, expect) \ if (sat_u_add_imm##IMM##_##T##_fmt_2(x) != expect) __builtin_abort () +#define RUN_SAT_U_ADD_IMM_FMT_3(T, x, IMM, expect) \ + if (sat_u_add_imm##IMM##_##T##_fmt_3(x) != expect) __builtin_abort () + /******************************************************************************/ /* Saturation Sub (Unsigned and Signed) */ /******************************************************************************/ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-10.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-10.c new file mode 100644 index 00000000000..24cdd267cca --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-10.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_add_imm3_uint16_t_fmt_3: +** addi\s+[atx][0-9]+,\s*a0,\s*3 +** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** slli\s+a0,\s*a0,\s*48 +** srli\s+a0,\s*a0,\s*48 +** ret +*/ +DEF_SAT_U_ADD_IMM_FMT_3(uint16_t, 3) + +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-11.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-11.c new file mode 100644 index 00000000000..f30e2405a0d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-11.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_add_imm7_uint32_t_fmt_3: +** addiw\s+[atx][0-9]+,\s*a0,\s*7 +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** sext.w\s+a0,\s*a0 +** ret +*/ +DEF_SAT_U_ADD_IMM_FMT_3(uint32_t, 7) + +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-12.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-12.c new file mode 100644 index 00000000000..561c127f5fa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-12.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_add_imm8_uint64_t_fmt_3: +** addi\s+[atx][0-9]+,\s*a0,\s*8 +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ +** ret +*/ +DEF_SAT_U_ADD_IMM_FMT_3(uint64_t, 8) + +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-9.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-9.c new file mode 100644 index 00000000000..5fcd6d71a26 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-9.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_add_imm9_uint8_t_fmt_3: +** addi\s+[atx][0-9]+,\s*a0,\s*9 +** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** andi\s+a0,\s*a0,\s*0xff +** ret +*/ +DEF_SAT_U_ADD_IMM_FMT_3(uint8_t, 9) + +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-10.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-10.c new file mode 100644 index 00000000000..64924a665a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-10.c @@ -0,0 +1,46 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_IMM_FMT_3(uint16_t, 0) +DEF_SAT_U_ADD_IMM_FMT_3(uint16_t, 1) +DEF_SAT_U_ADD_IMM_FMT_3(uint16_t, 65534) +DEF_SAT_U_ADD_IMM_FMT_3(uint16_t, 65535) + +#define T uint16_t +#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_3(T, op, imm, expect) + +T d[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 65534, 65534, }, + { 1, 65534, 65535, }, + { 2, 65534, 65535, }, + { 0, 65535, 65535, }, + { 1, 65535, 65535, }, + { 2, 65535, 65535, }, + { 65535, 65535, 65535, }, +}; + +int +main () +{ + RUN (T, d[0][0], 0, d[0][2]); + + RUN (T, d[1][0], 1, d[1][2]); + RUN (T, d[2][0], 1, d[2][2]); + + RUN (T, d[3][0], 65534, d[3][2]); + RUN (T, d[4][0], 65534, d[4][2]); + RUN (T, d[5][0], 65534, d[5][2]); + + RUN (T, d[6][0], 65535, d[6][2]); + RUN (T, d[7][0], 65535, d[7][2]); + RUN (T, d[8][0], 65535, d[8][2]); + RUN (T, d[9][0], 65535, d[9][2]); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-11.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-11.c new file mode 100644 index 00000000000..04f32172065 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-11.c @@ -0,0 +1,46 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_IMM_FMT_3(uint32_t, 0) +DEF_SAT_U_ADD_IMM_FMT_3(uint32_t, 1) +DEF_SAT_U_ADD_IMM_FMT_3(uint32_t, 4294967294) +DEF_SAT_U_ADD_IMM_FMT_3(uint32_t, 4294967295) + +#define T uint32_t +#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_3(T, op, imm, expect) + +T d[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 4294967294, 4294967294, }, + { 1, 4294967294, 4294967295, }, + { 2, 4294967294, 4294967295, }, + { 0, 4294967295, 4294967295, }, + { 1, 4294967295, 4294967295, }, + { 2, 4294967295, 4294967295, }, + { 4294967295, 4294967295, 4294967295, }, +}; + +int +main () +{ + RUN (T, d[0][0], 0, d[0][2]); + + RUN (T, d[1][0], 1, d[1][2]); + RUN (T, d[2][0], 1, d[2][2]); + + RUN (T, d[3][0], 4294967294, d[3][2]); + RUN (T, d[4][0], 4294967294, d[4][2]); + RUN (T, d[5][0], 4294967294, d[5][2]); + + RUN (T, d[6][0], 4294967295, d[6][2]); + RUN (T, d[7][0], 4294967295, d[7][2]); + RUN (T, d[8][0], 4294967295, d[8][2]); + RUN (T, d[9][0], 4294967295, d[9][2]); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-12.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-12.c new file mode 100644 index 00000000000..8ef6c14a367 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-12.c @@ -0,0 +1,46 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_IMM_FMT_3(uint64_t, 0) +DEF_SAT_U_ADD_IMM_FMT_3(uint64_t, 1) +DEF_SAT_U_ADD_IMM_FMT_3(uint64_t, 18446744073709551614u) +DEF_SAT_U_ADD_IMM_FMT_3(uint64_t, 18446744073709551615u) + +#define T uint64_t +#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_3(T, op, imm, expect) + +T d[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 18446744073709551614u, 18446744073709551614u, }, + { 1, 18446744073709551614u, 18446744073709551615u, }, + { 2, 18446744073709551614u, 18446744073709551615u, }, + { 0, 18446744073709551615u, 18446744073709551615u, }, + { 1, 18446744073709551615u, 18446744073709551615u, }, + { 2, 18446744073709551615u, 18446744073709551615u, }, + { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, }, +}; + +int +main () +{ + RUN (T, d[0][0], 0, d[0][2]); + + RUN (T, d[1][0], 1, d[1][2]); + RUN (T, d[2][0], 1, d[2][2]); + + RUN (T, d[3][0], 18446744073709551614u, d[3][2]); + RUN (T, d[4][0], 18446744073709551614u, d[4][2]); + RUN (T, d[5][0], 18446744073709551614u, d[5][2]); + + RUN (T, d[6][0], 18446744073709551615u, d[6][2]); + RUN (T, d[7][0], 18446744073709551615u, d[7][2]); + RUN (T, d[8][0], 18446744073709551615u, d[8][2]); + RUN (T, d[9][0], 18446744073709551615u, d[9][2]); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-9.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-9.c new file mode 100644 index 00000000000..88673610454 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-9.c @@ -0,0 +1,46 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_IMM_FMT_3(uint8_t, 0) +DEF_SAT_U_ADD_IMM_FMT_3(uint8_t, 1) +DEF_SAT_U_ADD_IMM_FMT_3(uint8_t, 254) +DEF_SAT_U_ADD_IMM_FMT_3(uint8_t, 255) + +#define T uint8_t +#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_3(T, op, imm, expect) + +T d[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 254, 254, }, + { 1, 254, 255, }, + { 2, 254, 255, }, + { 0, 255, 255, }, + { 1, 255, 255, }, + { 2, 255, 255, }, + { 255, 255, 255, }, +}; + +int +main () +{ + RUN (T, d[0][0], 0, d[0][2]); + + RUN (T, d[1][0], 1, d[1][2]); + RUN (T, d[2][0], 1, d[2][2]); + + RUN (T, d[3][0], 254, d[3][2]); + RUN (T, d[4][0], 254, d[4][2]); + RUN (T, d[5][0], 254, d[5][2]); + + RUN (T, d[6][0], 255, d[6][2]); + RUN (T, d[7][0], 255, d[7][2]); + RUN (T, d[8][0], 255, d[8][2]); + RUN (T, d[9][0], 255, d[9][2]); + + return 0; +}