From patchwork Mon Jul 1 01:35:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1954463 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=QluAbslJ; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4WC7tc1YKHz1xpT for ; Mon, 1 Jul 2024 11:36:40 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 76C71381D45D for ; Mon, 1 Jul 2024 01:36:38 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) by sourceware.org (Postfix) with ESMTPS id 8D3DA382FAF8 for ; Mon, 1 Jul 2024 01:35:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8D3DA382FAF8 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 8D3DA382FAF8 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.198.163.11 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1719797755; cv=none; b=k2F+Gv/VzFI4346YhXGmVIFtPPhJRlGZwRapZ4Ko/+WOi+CMI+elRvIZTz/3mqxaW74pa5ZDgzLtWK43evvvZUzqF35jEOdl1l6auABmTu59jQJKTVsZyxYcEwJFp8QyJy+vOYj9ddVOOvWiJx9vj68aQLUCX38WSv7UG1nTZdI= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1719797755; c=relaxed/simple; bh=LYM5whQ24zJS+OfbdYNqqy0+iDI/ap8+WGG1kTUiXMw=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=WjyC4tGSV0rvg7+pE+kY6tTGXqx/lCMJvqAnRLTAk7GvNPPzBCBtMZ6voBK615XG94Oxf+OuRF+FYy6PFrbPmi9kCM1EFIXQgMq0Bg7iGhaidyWWcr4t7SJT1Ou9upTtFLdq07cOvyInIqmAKw78/7L+tfpJLSzkqxxxOiJx6B8= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719797753; x=1751333753; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LYM5whQ24zJS+OfbdYNqqy0+iDI/ap8+WGG1kTUiXMw=; b=QluAbslJR+kh/5EuKvuhGkGDFGRIA/VVJCpXBs+dOW+zv64BfgQO+WS6 BLsHipzmxm4HTLCY05fZpwPMkrAQ9rb0nT67NEYM3WfQswZ/Wy5SwS450 Pc64Sc5DCIgJ1PBKIJ1MxwY6J6mpnTUA27F2aiXYVlcTpJTzs+HgCrSNS CSm/GoYTGC/+pcR1S+2/OaHrFQLz+vP4abok0zzL7/A0GLLjKP7L238dB 53KmI9kkm7UVNWkkU0h0vsTZGCVaXicXgtabmEFeu1SBbmriGtkXSoBvm VP3gBt13+eORKoVQPR1QB3ou22v39RR2MiB+H8t//X+EmiYovjb46Ubm6 w==; X-CSE-ConnectionGUID: EZmVUirpRb28YV9ptTFWkA== X-CSE-MsgGUID: sdPKYr7lRBijW28Zt1RCxA== X-IronPort-AV: E=McAfee;i="6700,10204,11119"; a="27520909" X-IronPort-AV: E=Sophos;i="6.09,175,1716274800"; d="scan'208";a="27520909" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jun 2024 18:35:47 -0700 X-CSE-ConnectionGUID: z089DxY+SG2upy+kuHIMYA== X-CSE-MsgGUID: y7JejxSwRwOOU46WwBH4JA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,175,1716274800"; d="scan'208";a="76524332" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmviesa001.fm.intel.com with ESMTP; 30 Jun 2024 18:35:44 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 048AE1007355; Mon, 1 Jul 2024 09:35:43 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v1 2/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 2 Date: Mon, 1 Jul 2024 09:35:37 +0800 Message-Id: <20240701013539.776849-2-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240701013539.776849-1-pan2.li@intel.com> References: <20240701013539.776849-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_LOTSOFHASH, KAM_NUMSUBJECT, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li This patch would like to add test cases for the unsigned scalar .SAT_ADD IMM form 2. Aka: Form 2: #define DEF_SAT_U_ADD_IMM_FMT_2(T) \ T __attribute__((noinline)) \ sat_u_add_imm_##T##_fmt_1 (T x) \ { \ return (T)(x + 9) < x ? -1 : (x + 9); \ } DEF_SAT_U_ADD_IMM_FMT_2(uint64_t) The below test is passed for this patch. * The rv64gcv regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_arith.h: Add helper test macro. * gcc.target/riscv/sat_u_add_imm-5.c: New test. * gcc.target/riscv/sat_u_add_imm-6.c: New test. * gcc.target/riscv/sat_u_add_imm-7.c: New test. * gcc.target/riscv/sat_u_add_imm-8.c: New test. * gcc.target/riscv/sat_u_add_imm-run-5.c: New test. * gcc.target/riscv/sat_u_add_imm-run-6.c: New test. * gcc.target/riscv/sat_u_add_imm-run-7.c: New test. * gcc.target/riscv/sat_u_add_imm-run-8.c: New test. Signed-off-by: Pan Li Signed-off-by: Pan Li --- gcc/testsuite/gcc.target/riscv/sat_arith.h | 10 ++++ .../gcc.target/riscv/sat_u_add_imm-5.c | 19 ++++++++ .../gcc.target/riscv/sat_u_add_imm-6.c | 21 +++++++++ .../gcc.target/riscv/sat_u_add_imm-7.c | 18 ++++++++ .../gcc.target/riscv/sat_u_add_imm-8.c | 17 +++++++ .../gcc.target/riscv/sat_u_add_imm-run-5.c | 46 +++++++++++++++++++ .../gcc.target/riscv/sat_u_add_imm-run-6.c | 46 +++++++++++++++++++ .../gcc.target/riscv/sat_u_add_imm-run-7.c | 46 +++++++++++++++++++ .../gcc.target/riscv/sat_u_add_imm-run-8.c | 46 +++++++++++++++++++ 9 files changed, 269 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-8.c diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h index 4ec4ec36cc1..d94f0fd602c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h @@ -67,9 +67,19 @@ sat_u_add_imm##IMM##_##T##_fmt_1 (T x) \ return (T)(x + IMM) >= x ? (x + IMM) : -1; \ } +#define DEF_SAT_U_ADD_IMM_FMT_2(T, IMM) \ +T __attribute__((noinline)) \ +sat_u_add_imm##IMM##_##T##_fmt_2 (T x) \ +{ \ + return (T)(x + IMM) < x ? -1 : (x + IMM); \ +} + #define RUN_SAT_U_ADD_IMM_FMT_1(T, x, IMM, expect) \ if (sat_u_add_imm##IMM##_##T##_fmt_1(x) != expect) __builtin_abort () +#define RUN_SAT_U_ADD_IMM_FMT_2(T, x, IMM, expect) \ + if (sat_u_add_imm##IMM##_##T##_fmt_2(x) != expect) __builtin_abort () + /******************************************************************************/ /* Saturation Sub (Unsigned and Signed) */ /******************************************************************************/ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-5.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-5.c new file mode 100644 index 00000000000..19b502db6c9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-5.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_add_imm9_uint8_t_fmt_2: +** addi\s+[atx][0-9]+,\s*a0,\s*9 +** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** andi\s+a0,\s*a0,\s*0xff +** ret +*/ +DEF_SAT_U_ADD_IMM_FMT_2(uint8_t, 9) + +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-6.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-6.c new file mode 100644 index 00000000000..0317370b67e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-6.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_add_imm3_uint16_t_fmt_2: +** addi\s+[atx][0-9]+,\s*a0,\s*3 +** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** slli\s+a0,\s*a0,\s*48 +** srli\s+a0,\s*a0,\s*48 +** ret +*/ +DEF_SAT_U_ADD_IMM_FMT_2(uint16_t, 3) + +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-7.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-7.c new file mode 100644 index 00000000000..044b821f7b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-7.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_add_imm7_uint32_t_fmt_2: +** addiw\s+[atx][0-9]+,\s*a0,\s*7 +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** sext.w\s+a0,\s*a0 +** ret +*/ +DEF_SAT_U_ADD_IMM_FMT_2(uint32_t, 7) + +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-8.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-8.c new file mode 100644 index 00000000000..4eafb83c756 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-8.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_add_imm8_uint64_t_fmt_2: +** addi\s+[atx][0-9]+,\s*a0,\s*8 +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ +** ret +*/ +DEF_SAT_U_ADD_IMM_FMT_2(uint64_t, 8) + +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-5.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-5.c new file mode 100644 index 00000000000..8e8759c9825 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-5.c @@ -0,0 +1,46 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_IMM_FMT_2(uint8_t, 0) +DEF_SAT_U_ADD_IMM_FMT_2(uint8_t, 1) +DEF_SAT_U_ADD_IMM_FMT_2(uint8_t, 254) +DEF_SAT_U_ADD_IMM_FMT_2(uint8_t, 255) + +#define T uint8_t +#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_2(T, op, imm, expect) + +T d[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 254, 254, }, + { 1, 254, 255, }, + { 2, 254, 255, }, + { 0, 255, 255, }, + { 1, 255, 255, }, + { 2, 255, 255, }, + { 255, 255, 255, }, +}; + +int +main () +{ + RUN (T, d[0][0], 0, d[0][2]); + + RUN (T, d[1][0], 1, d[1][2]); + RUN (T, d[2][0], 1, d[2][2]); + + RUN (T, d[3][0], 254, d[3][2]); + RUN (T, d[4][0], 254, d[4][2]); + RUN (T, d[5][0], 254, d[5][2]); + + RUN (T, d[6][0], 255, d[6][2]); + RUN (T, d[7][0], 255, d[7][2]); + RUN (T, d[8][0], 255, d[8][2]); + RUN (T, d[9][0], 255, d[9][2]); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-6.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-6.c new file mode 100644 index 00000000000..7b6bd731234 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-6.c @@ -0,0 +1,46 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_IMM_FMT_2(uint16_t, 0) +DEF_SAT_U_ADD_IMM_FMT_2(uint16_t, 1) +DEF_SAT_U_ADD_IMM_FMT_2(uint16_t, 65534) +DEF_SAT_U_ADD_IMM_FMT_2(uint16_t, 65535) + +#define T uint16_t +#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_2(T, op, imm, expect) + +T d[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 65534, 65534, }, + { 1, 65534, 65535, }, + { 2, 65534, 65535, }, + { 0, 65535, 65535, }, + { 1, 65535, 65535, }, + { 2, 65535, 65535, }, + { 65535, 65535, 65535, }, +}; + +int +main () +{ + RUN (T, d[0][0], 0, d[0][2]); + + RUN (T, d[1][0], 1, d[1][2]); + RUN (T, d[2][0], 1, d[2][2]); + + RUN (T, d[3][0], 65534, d[3][2]); + RUN (T, d[4][0], 65534, d[4][2]); + RUN (T, d[5][0], 65534, d[5][2]); + + RUN (T, d[6][0], 65535, d[6][2]); + RUN (T, d[7][0], 65535, d[7][2]); + RUN (T, d[8][0], 65535, d[8][2]); + RUN (T, d[9][0], 65535, d[9][2]); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-7.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-7.c new file mode 100644 index 00000000000..80241527ee9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-7.c @@ -0,0 +1,46 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_IMM_FMT_2(uint32_t, 0) +DEF_SAT_U_ADD_IMM_FMT_2(uint32_t, 1) +DEF_SAT_U_ADD_IMM_FMT_2(uint32_t, 4294967294) +DEF_SAT_U_ADD_IMM_FMT_2(uint32_t, 4294967295) + +#define T uint32_t +#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_2(T, op, imm, expect) + +T d[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 4294967294, 4294967294, }, + { 1, 4294967294, 4294967295, }, + { 2, 4294967294, 4294967295, }, + { 0, 4294967295, 4294967295, }, + { 1, 4294967295, 4294967295, }, + { 2, 4294967295, 4294967295, }, + { 4294967295, 4294967295, 4294967295, }, +}; + +int +main () +{ + RUN (T, d[0][0], 0, d[0][2]); + + RUN (T, d[1][0], 1, d[1][2]); + RUN (T, d[2][0], 1, d[2][2]); + + RUN (T, d[3][0], 4294967294, d[3][2]); + RUN (T, d[4][0], 4294967294, d[4][2]); + RUN (T, d[5][0], 4294967294, d[5][2]); + + RUN (T, d[6][0], 4294967295, d[6][2]); + RUN (T, d[7][0], 4294967295, d[7][2]); + RUN (T, d[8][0], 4294967295, d[8][2]); + RUN (T, d[9][0], 4294967295, d[9][2]); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-8.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-8.c new file mode 100644 index 00000000000..4a76dbb6dde --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-8.c @@ -0,0 +1,46 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_IMM_FMT_2(uint64_t, 0) +DEF_SAT_U_ADD_IMM_FMT_2(uint64_t, 1) +DEF_SAT_U_ADD_IMM_FMT_2(uint64_t, 18446744073709551614u) +DEF_SAT_U_ADD_IMM_FMT_2(uint64_t, 18446744073709551615u) + +#define T uint64_t +#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_2(T, op, imm, expect) + +T d[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 18446744073709551614u, 18446744073709551614u, }, + { 1, 18446744073709551614u, 18446744073709551615u, }, + { 2, 18446744073709551614u, 18446744073709551615u, }, + { 0, 18446744073709551615u, 18446744073709551615u, }, + { 1, 18446744073709551615u, 18446744073709551615u, }, + { 2, 18446744073709551615u, 18446744073709551615u, }, + { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, }, +}; + +int +main () +{ + RUN (T, d[0][0], 0, d[0][2]); + + RUN (T, d[1][0], 1, d[1][2]); + RUN (T, d[2][0], 1, d[2][2]); + + RUN (T, d[3][0], 18446744073709551614u, d[3][2]); + RUN (T, d[4][0], 18446744073709551614u, d[4][2]); + RUN (T, d[5][0], 18446744073709551614u, d[5][2]); + + RUN (T, d[6][0], 18446744073709551615u, d[6][2]); + RUN (T, d[7][0], 18446744073709551615u, d[7][2]); + RUN (T, d[8][0], 18446744073709551615u, d[8][2]); + RUN (T, d[9][0], 18446744073709551615u, d[9][2]); + + return 0; +}