From patchwork Thu Jun 27 08:23:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Hongtao" X-Patchwork-Id: 1953049 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=A0itEMp4; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4W8sJC3xmHz20X6 for ; Thu, 27 Jun 2024 18:32:27 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C6DD43838A21 for ; Thu, 27 Jun 2024 08:32:25 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) by sourceware.org (Postfix) with ESMTPS id B0694383939A for ; Thu, 27 Jun 2024 08:23:43 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B0694383939A Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org B0694383939A Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1719476643; cv=none; b=cur30Cag60qG/mpKuMOJ2kXJEOQNwVQ6xMawjltzrVg7Dn/jyuhn0TpJc8KG7I8puWjkpl+yYAhKFYTP4A86otPniXEuz4744Y+1OnhoO4mp+MfhM2/696D+vwjQgpK5jXANXk6K39leW/iVKZWbbm21TMJiIthYGL69d7k7BzE= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1719476643; c=relaxed/simple; bh=hFqWEBa3h+IqN5is3MOZFyylnt2XRjTNXU6HcuNqCvw=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=sbFi1A2PgSKWHdx7j49wT25W9IoMw43JpzgqLBoYOYJRRi9Ki5/iYykE0RZv5wv1S/jldfMj+oYRupglePc2suo5Bmaoj8TfdmSQ/j4bVaCB7u6LU6wK1i8JmM2qYB6lSfSMzt/xWO+EABdAgJTPlVYkG0ps1wDED+SXB4pDM5I= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719476624; x=1751012624; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hFqWEBa3h+IqN5is3MOZFyylnt2XRjTNXU6HcuNqCvw=; b=A0itEMp4OB9rcNaTg77SKbz/9PPCGl3/v0+cl5VaGu8642Zu38pnuGs5 OpZd192uee0YH4U8w1dk2pOp2g1UcoyvBqx736e/1vnB1UZ/SONWaQ1Yt l8CBpBeeoaAR3colBNeT3WtawHxCPnp/qwM56Vj17bfaw4OD0v9sEXZCJ mVqzlGjjR2El1Fp+VJ0cFyuUhiEefGNDy0hDpeVTVNuHgLEMNUG1NqDtm aJLbT+GXNRo0+LVIc5Sr3KpOEdsqVDmYdn03XnFFfxfqQHqURuZh3NziC sDRRRR6Mp5LFCQsCzWRje7CveTAr7wlTQ4JBU5oOjxxZNDxsm5F76Z47t Q==; X-CSE-ConnectionGUID: XeJNbumNTRik80ii+r8/zQ== X-CSE-MsgGUID: 3lfv0G+WRROflsys6D6JWA== X-IronPort-AV: E=McAfee;i="6700,10204,11115"; a="16732327" X-IronPort-AV: E=Sophos;i="6.08,269,1712646000"; d="scan'208";a="16732327" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2024 01:23:15 -0700 X-CSE-ConnectionGUID: /Ll6m0eJTkybwVGam1QJGQ== X-CSE-MsgGUID: miDDdHplSPGtHYpAInTJ3Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,269,1712646000"; d="scan'208";a="44944368" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orviesa007.jf.intel.com with ESMTP; 27 Jun 2024 01:23:10 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id A23791007359; Thu, 27 Jun 2024 16:23:07 +0800 (CST) From: liuhongt To: gcc-patches@gcc.gnu.org Cc: crazylht@gmail.com, hjl.tools@gmail.com Subject: [PATCH 7/7] Remove vcond{, u, eq} expanders since they will be obsolete. Date: Thu, 27 Jun 2024 16:23:07 +0800 Message-Id: <20240627082307.1166985-8-hongtao.liu@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20240627082307.1166985-1-hongtao.liu@intel.com> References: <20240627082307.1166985-1-hongtao.liu@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org gcc/ChangeLog: PR target/115517 * config/i386/mmx.md (vcondv2sf): Removed. (vcond): Ditto. (vcond): Ditto. (vcondu): Ditto. (vcondu): Ditto. * config/i386/sse.md (vcond): Ditto. (vcond): Ditto. (vcond): Ditto. (vcond): Ditto. (vcond): Ditto. (vcond): Ditto. (vcond): Ditto. (vcondv2di): Ditto. (vcondu): Ditto. (vcondu): Ditto. (vcondu): Ditto. (vconduv2di): Ditto. (vcondeqv2di): Ditto. --- gcc/config/i386/mmx.md | 97 ------------------- gcc/config/i386/sse.md | 213 ----------------------------------------- 2 files changed, 310 deletions(-) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 7262bf146c2..17c5205cae2 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1168,39 +1168,6 @@ (define_expand "vec_cmpv2sfv2si" DONE; }) -(define_expand "vcondv2sf" - [(set (match_operand:V2FI 0 "register_operand") - (if_then_else:V2FI - (match_operator 3 "" - [(match_operand:V2SF 4 "nonimmediate_operand") - (match_operand:V2SF 5 "nonimmediate_operand")]) - (match_operand:V2FI 1 "general_operand") - (match_operand:V2FI 2 "general_operand")))] - "TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math" -{ - rtx ops[6]; - ops[5] = gen_reg_rtx (V4SFmode); - ops[4] = gen_reg_rtx (V4SFmode); - ops[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), VOIDmode, ops[4], ops[5]); - ops[2] = lowpart_subreg (mode, - force_reg (mode, operands[2]), - mode); - ops[1] = lowpart_subreg (mode, - force_reg (mode, operands[1]), - mode); - ops[0] = gen_reg_rtx (mode); - - emit_insn (gen_movq_v2sf_to_sse (ops[5], operands[5])); - emit_insn (gen_movq_v2sf_to_sse (ops[4], operands[4])); - - bool ok = ix86_expand_fp_vcond (ops); - gcc_assert (ok); - - emit_move_insn (operands[0], lowpart_subreg (mode, ops[0], - mode)); - DONE; -}) - (define_insn "@sse4_1_insertps_" [(set (match_operand:V2FI 0 "register_operand" "=Yr,*x,v") (unspec:V2FI @@ -4029,70 +3996,6 @@ (define_expand "vec_cmpu" DONE; }) -(define_expand "vcond" - [(set (match_operand:MMXMODE124 0 "register_operand") - (if_then_else:MMXMODE124 - (match_operator 3 "" - [(match_operand:MMXMODEI 4 "register_operand") - (match_operand:MMXMODEI 5 "register_operand")]) - (match_operand:MMXMODE124 1) - (match_operand:MMXMODE124 2)))] - "TARGET_MMX_WITH_SSE - && (GET_MODE_NUNITS (mode) - == GET_MODE_NUNITS (mode))" -{ - bool ok = ix86_expand_int_vcond (operands); - gcc_assert (ok); - DONE; -}) - -(define_expand "vcond" - [(set (match_operand:VI_16_32 0 "register_operand") - (if_then_else:VI_16_32 - (match_operator 3 "" - [(match_operand:VI_16_32 4 "register_operand") - (match_operand:VI_16_32 5 "register_operand")]) - (match_operand:VI_16_32 1) - (match_operand:VI_16_32 2)))] - "TARGET_SSE2" -{ - bool ok = ix86_expand_int_vcond (operands); - gcc_assert (ok); - DONE; -}) - -(define_expand "vcondu" - [(set (match_operand:MMXMODE124 0 "register_operand") - (if_then_else:MMXMODE124 - (match_operator 3 "" - [(match_operand:MMXMODEI 4 "register_operand") - (match_operand:MMXMODEI 5 "register_operand")]) - (match_operand:MMXMODE124 1) - (match_operand:MMXMODE124 2)))] - "TARGET_MMX_WITH_SSE - && (GET_MODE_NUNITS (mode) - == GET_MODE_NUNITS (mode))" -{ - bool ok = ix86_expand_int_vcond (operands); - gcc_assert (ok); - DONE; -}) - -(define_expand "vcondu" - [(set (match_operand:VI_16_32 0 "register_operand") - (if_then_else:VI_16_32 - (match_operator 3 "" - [(match_operand:VI_16_32 4 "register_operand") - (match_operand:VI_16_32 5 "register_operand")]) - (match_operand:VI_16_32 1) - (match_operand:VI_16_32 2)))] - "TARGET_SSE2" -{ - bool ok = ix86_expand_int_vcond (operands); - gcc_assert (ok); - DONE; -}) - (define_expand "vcond_mask_" [(set (match_operand:MMXMODE124 0 "register_operand") (vec_merge:MMXMODE124 diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index d86b6fa81c0..2d6b39c920f 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -4816,72 +4816,6 @@ (define_expand "vec_cmpeqv1tiv1ti" DONE; }) -(define_expand "vcond" - [(set (match_operand:V_512 0 "register_operand") - (if_then_else:V_512 - (match_operator 3 "" - [(match_operand:VF_512 4 "nonimmediate_operand") - (match_operand:VF_512 5 "nonimmediate_operand")]) - (match_operand:V_512 1 "general_operand") - (match_operand:V_512 2 "general_operand")))] - "TARGET_AVX512F - && (GET_MODE_NUNITS (mode) - == GET_MODE_NUNITS (mode))" -{ - bool ok = ix86_expand_fp_vcond (operands); - gcc_assert (ok); - DONE; -}) - -(define_expand "vcond" - [(set (match_operand:V_256 0 "register_operand") - (if_then_else:V_256 - (match_operator 3 "" - [(match_operand:VF_256 4 "nonimmediate_operand") - (match_operand:VF_256 5 "nonimmediate_operand")]) - (match_operand:V_256 1 "general_operand") - (match_operand:V_256 2 "general_operand")))] - "TARGET_AVX - && (GET_MODE_NUNITS (mode) - == GET_MODE_NUNITS (mode))" -{ - bool ok = ix86_expand_fp_vcond (operands); - gcc_assert (ok); - DONE; -}) - -(define_expand "vcond" - [(set (match_operand:V_128 0 "register_operand") - (if_then_else:V_128 - (match_operator 3 "" - [(match_operand:VF_128 4 "vector_operand") - (match_operand:VF_128 5 "vector_operand")]) - (match_operand:V_128 1 "general_operand") - (match_operand:V_128 2 "general_operand")))] - "TARGET_SSE - && (GET_MODE_NUNITS (mode) - == GET_MODE_NUNITS (mode))" -{ - bool ok = ix86_expand_fp_vcond (operands); - gcc_assert (ok); - DONE; -}) - -(define_expand "vcond" - [(set (match_operand:VI2HFBF_AVX512VL 0 "register_operand") - (if_then_else:VI2HFBF_AVX512VL - (match_operator 3 "" - [(match_operand:VHF_AVX512VL 4 "vector_operand") - (match_operand:VHF_AVX512VL 5 "vector_operand")]) - (match_operand:VI2HFBF_AVX512VL 1 "general_operand") - (match_operand:VI2HFBF_AVX512VL 2 "general_operand")))] - "TARGET_AVX512FP16" -{ - bool ok = ix86_expand_fp_vcond (operands); - gcc_assert (ok); - DONE; -}) - (define_expand "vcond_mask_" [(set (match_operand:V48_AVX512VL 0 "register_operand") (vec_merge:V48_AVX512VL @@ -18017,153 +17951,6 @@ (define_insn "*sse2_gt3" (set_attr "prefix" "orig,vex") (set_attr "mode" "TI")]) -(define_expand "vcond" - [(set (match_operand:V_512 0 "register_operand") - (if_then_else:V_512 - (match_operator 3 "" - [(match_operand:VI_AVX512BW 4 "nonimmediate_operand") - (match_operand:VI_AVX512BW 5 "general_operand")]) - (match_operand:V_512 1) - (match_operand:V_512 2)))] - "TARGET_AVX512F - && (GET_MODE_NUNITS (mode) - == GET_MODE_NUNITS (mode))" -{ - bool ok = ix86_expand_int_vcond (operands); - gcc_assert (ok); - DONE; -}) - -(define_expand "vcond" - [(set (match_operand:V_256 0 "register_operand") - (if_then_else:V_256 - (match_operator 3 "" - [(match_operand:VI_256 4 "nonimmediate_operand") - (match_operand:VI_256 5 "general_operand")]) - (match_operand:V_256 1) - (match_operand:V_256 2)))] - "TARGET_AVX2 - && (GET_MODE_NUNITS (mode) - == GET_MODE_NUNITS (mode))" -{ - bool ok = ix86_expand_int_vcond (operands); - gcc_assert (ok); - DONE; -}) - -(define_expand "vcond" - [(set (match_operand:V_128 0 "register_operand") - (if_then_else:V_128 - (match_operator 3 "" - [(match_operand:VI124_128 4 "vector_operand") - (match_operand:VI124_128 5 "general_operand")]) - (match_operand:V_128 1) - (match_operand:V_128 2)))] - "TARGET_SSE2 - && (GET_MODE_NUNITS (mode) - == GET_MODE_NUNITS (mode))" -{ - bool ok = ix86_expand_int_vcond (operands); - gcc_assert (ok); - DONE; -}) - -(define_expand "vcondv2di" - [(set (match_operand:VI8F_128 0 "register_operand") - (if_then_else:VI8F_128 - (match_operator 3 "" - [(match_operand:V2DI 4 "vector_operand") - (match_operand:V2DI 5 "general_operand")]) - (match_operand:VI8F_128 1) - (match_operand:VI8F_128 2)))] - "TARGET_SSE4_2" -{ - bool ok = ix86_expand_int_vcond (operands); - gcc_assert (ok); - DONE; -}) - -(define_expand "vcondu" - [(set (match_operand:V_512 0 "register_operand") - (if_then_else:V_512 - (match_operator 3 "" - [(match_operand:VI_AVX512BW 4 "nonimmediate_operand") - (match_operand:VI_AVX512BW 5 "nonimmediate_operand")]) - (match_operand:V_512 1 "general_operand") - (match_operand:V_512 2 "general_operand")))] - "TARGET_AVX512F - && (GET_MODE_NUNITS (mode) - == GET_MODE_NUNITS (mode))" -{ - bool ok = ix86_expand_int_vcond (operands); - gcc_assert (ok); - DONE; -}) - -(define_expand "vcondu" - [(set (match_operand:V_256 0 "register_operand") - (if_then_else:V_256 - (match_operator 3 "" - [(match_operand:VI_256 4 "nonimmediate_operand") - (match_operand:VI_256 5 "nonimmediate_operand")]) - (match_operand:V_256 1 "general_operand") - (match_operand:V_256 2 "general_operand")))] - "TARGET_AVX2 - && (GET_MODE_NUNITS (mode) - == GET_MODE_NUNITS (mode))" -{ - bool ok = ix86_expand_int_vcond (operands); - gcc_assert (ok); - DONE; -}) - -(define_expand "vcondu" - [(set (match_operand:V_128 0 "register_operand") - (if_then_else:V_128 - (match_operator 3 "" - [(match_operand:VI124_128 4 "vector_operand") - (match_operand:VI124_128 5 "vector_operand")]) - (match_operand:V_128 1 "general_operand") - (match_operand:V_128 2 "general_operand")))] - "TARGET_SSE2 - && (GET_MODE_NUNITS (mode) - == GET_MODE_NUNITS (mode))" -{ - bool ok = ix86_expand_int_vcond (operands); - gcc_assert (ok); - DONE; -}) - -(define_expand "vconduv2di" - [(set (match_operand:VI8F_128 0 "register_operand") - (if_then_else:VI8F_128 - (match_operator 3 "" - [(match_operand:V2DI 4 "vector_operand") - (match_operand:V2DI 5 "vector_operand")]) - (match_operand:VI8F_128 1 "general_operand") - (match_operand:VI8F_128 2 "general_operand")))] - "TARGET_SSE4_2" -{ - bool ok = ix86_expand_int_vcond (operands); - gcc_assert (ok); - DONE; -}) - -(define_expand "vcondeqv2di" - [(set (match_operand:VI8F_128 0 "register_operand") - (if_then_else:VI8F_128 - (match_operator 3 "" - [(match_operand:V2DI 4 "vector_operand") - (match_operand:V2DI 5 "general_operand")]) - (match_operand:VI8F_128 1) - (match_operand:VI8F_128 2)))] - "TARGET_SSE4_1" -{ - bool ok = ix86_expand_int_vcond (operands); - gcc_assert (ok); - DONE; -}) - (define_mode_iterator VEC_PERM_AVX2 [V16QI V8HI V4SI V2DI V4SF V2DF (V8HF "TARGET_AVX512FP16")