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Tue, 18 Jun 2024 02:26:23 -0700 (PDT) Received: from localhost.localdomain ([194.169.55.179]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f855f01a26sm93216125ad.199.2024.06.18.02.26.22 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 18 Jun 2024 02:26:23 -0700 (PDT) From: YunQiang Su To: gcc-patches@gcc.gnu.org Cc: YunQiang Su Subject: [PATCH] MIPS: Set condmove cost to SET(REG, REG) Date: Tue, 18 Jun 2024 17:26:18 +0800 Message-Id: <20240618092618.90160-1-syq@gcc.gnu.org> X-Mailer: git-send-email 2.39.3 (Apple Git-146) MIME-Version: 1.0 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org On most uarch, the cost condmove is same as other noraml integer, and it should be COSTS_N_INSNS(1). In GCC12 or previous, the condmove is always enabled, and from GCC13, we start to compare the cost. The generic rtx_cost give the result of COSTS_N_INSN(2). Let's define it to COSTS_N_INSN(1) in mips_rtx_costs. gcc * config/mips/mips.cc(mips_rtx_costs): Set condmove cost. * config/mips/mips.md(mov_on_, mov_on__mips16e2, mov_on__ne mov_on__ne_mips16e2): Define name by remove starting *, so that we can use CODE_FOR_. gcc/testsute * gcc.target/mips/movcc-2.c: Add k?100:1000 test. --- gcc/config/mips/mips.cc | 24 ++++++++++++++++++++++++ gcc/config/mips/mips.md | 8 ++++---- gcc/testsuite/gcc.target/mips/movcc-2.c | 14 ++++++++++++++ 3 files changed, 42 insertions(+), 4 deletions(-) diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index b7acf041903..48924116937 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -4692,6 +4692,30 @@ mips_rtx_costs (rtx x, machine_mode mode, int outer_code, *total = mips_set_reg_reg_cost (GET_MODE (SET_DEST (x))); return true; } + int insn_code; + if (register_operand (SET_DEST (x), VOIDmode) + && GET_CODE (SET_SRC (x)) == IF_THEN_ELSE) + insn_code = recog_memoized (make_insn_raw (x)); + else + insn_code = -1; + switch (insn_code) + { + /* MIPS16e2 ones may be listed here, while the only known CPU core + that implements MIPS16e2 is interAptiv. The Dependency delays + of MOVN/MOVZ on interAptiv is 3. */ + case CODE_FOR_movsi_on_si: + case CODE_FOR_movdi_on_si: + case CODE_FOR_movsi_on_di: + case CODE_FOR_movdi_on_di: + case CODE_FOR_movsi_on_si_ne: + case CODE_FOR_movdi_on_si_ne: + case CODE_FOR_movsi_on_di_ne: + case CODE_FOR_movdi_on_di_ne: + *total = mips_set_reg_reg_cost (GET_MODE (SET_DEST (x))); + return true; + default: + break; + } return false; default: diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 508fb1afa6c..9962313602a 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -7492,7 +7492,7 @@ (define_insn "insn_pseudo" ;; MIPS4 Conditional move instructions. -(define_insn "*mov_on_" +(define_insn "mov_on_" [(set (match_operand:GPR 0 "register_operand" "=d,d") (if_then_else:GPR (match_operator 4 "equality_operator" @@ -7507,7 +7507,7 @@ (define_insn "*mov_on_" [(set_attr "type" "condmove") (set_attr "mode" "")]) -(define_insn "*mov_on__mips16e2" +(define_insn "mov_on__mips16e2" [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d") (if_then_else:GPR (match_operator 4 "equality_operator" @@ -7525,7 +7525,7 @@ (define_insn "*mov_on__mips16e2" (set_attr "mode" "") (set_attr "extended_mips16" "yes")]) -(define_insn "*mov_on__ne" +(define_insn "mov_on__ne" [(set (match_operand:GPR 0 "register_operand" "=d,d") (if_then_else:GPR (match_operand:GPR2 1 "register_operand" ",") @@ -7538,7 +7538,7 @@ (define_insn "*mov_on__ne" [(set_attr "type" "condmove") (set_attr "mode" "")]) -(define_insn "*mov_on__ne_mips16e2" +(define_insn "mov_on__ne_mips16e2" [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d") (if_then_else:GPR (match_operand:GPR2 1 "register_operand" ",,t,t") diff --git a/gcc/testsuite/gcc.target/mips/movcc-2.c b/gcc/testsuite/gcc.target/mips/movcc-2.c index 1926e6460d1..cbda3c8febc 100644 --- a/gcc/testsuite/gcc.target/mips/movcc-2.c +++ b/gcc/testsuite/gcc.target/mips/movcc-2.c @@ -3,6 +3,8 @@ /* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ /* { dg-final { scan-assembler "\tmovz\t" } } */ /* { dg-final { scan-assembler "\tmovn\t" } } */ +/* { dg-final { scan-assembler "\tmovz\t" } } */ +/* { dg-final { scan-assembler "\tmovn\t" } } */ void ext_long (long); @@ -17,3 +19,15 @@ sub5 (long i, long j, int k) { ext_long (!k ? i : j); } + +NOMIPS16 long +sub6 (int k) +{ + return !k ? 100 : 1000; +} + +NOMIPS16 long +sub7 (int k) +{ + return !k ? 100 : 1000; +}