@@ -4692,6 +4692,30 @@ mips_rtx_costs (rtx x, machine_mode mode, int outer_code,
*total = mips_set_reg_reg_cost (GET_MODE (SET_DEST (x)));
return true;
}
+ int insn_code;
+ if (register_operand (SET_DEST (x), VOIDmode)
+ && GET_CODE (SET_SRC (x)) == IF_THEN_ELSE)
+ insn_code = recog_memoized (make_insn_raw (x));
+ else
+ insn_code = -1;
+ switch (insn_code)
+ {
+ /* MIPS16e2 ones may be listed here, while the only known CPU core
+ that implements MIPS16e2 is interAptiv. The Dependency delays
+ of MOVN/MOVZ on interAptiv is 3. */
+ case CODE_FOR_movsi_on_si:
+ case CODE_FOR_movdi_on_si:
+ case CODE_FOR_movsi_on_di:
+ case CODE_FOR_movdi_on_di:
+ case CODE_FOR_movsi_on_si_ne:
+ case CODE_FOR_movdi_on_si_ne:
+ case CODE_FOR_movsi_on_di_ne:
+ case CODE_FOR_movdi_on_di_ne:
+ *total = mips_set_reg_reg_cost (GET_MODE (SET_DEST (x)));
+ return true;
+ default:
+ break;
+ }
return false;
default:
@@ -7492,7 +7492,7 @@ (define_insn "insn_pseudo"
;; MIPS4 Conditional move instructions.
-(define_insn "*mov<GPR:mode>_on_<MOVECC:mode>"
+(define_insn "mov<GPR:mode>_on_<MOVECC:mode>"
[(set (match_operand:GPR 0 "register_operand" "=d,d")
(if_then_else:GPR
(match_operator 4 "equality_operator"
@@ -7507,7 +7507,7 @@ (define_insn "*mov<GPR:mode>_on_<MOVECC:mode>"
[(set_attr "type" "condmove")
(set_attr "mode" "<GPR:MODE>")])
-(define_insn "*mov<GPR:mode>_on_<MOVECC:mode>_mips16e2"
+(define_insn "mov<GPR:mode>_on_<MOVECC:mode>_mips16e2"
[(set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
(if_then_else:GPR
(match_operator 4 "equality_operator"
@@ -7525,7 +7525,7 @@ (define_insn "*mov<GPR:mode>_on_<MOVECC:mode>_mips16e2"
(set_attr "mode" "<GPR:MODE>")
(set_attr "extended_mips16" "yes")])
-(define_insn "*mov<GPR:mode>_on_<GPR2:mode>_ne"
+(define_insn "mov<GPR:mode>_on_<GPR2:mode>_ne"
[(set (match_operand:GPR 0 "register_operand" "=d,d")
(if_then_else:GPR
(match_operand:GPR2 1 "register_operand" "<GPR2:reg>,<GPR2:reg>")
@@ -7538,7 +7538,7 @@ (define_insn "*mov<GPR:mode>_on_<GPR2:mode>_ne"
[(set_attr "type" "condmove")
(set_attr "mode" "<GPR:MODE>")])
-(define_insn "*mov<GPR:mode>_on_<GPR2:mode>_ne_mips16e2"
+(define_insn "mov<GPR:mode>_on_<GPR2:mode>_ne_mips16e2"
[(set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
(if_then_else:GPR
(match_operand:GPR2 1 "register_operand" "<GPR2:reg>,<GPR2:reg>,t,t")
@@ -3,6 +3,8 @@
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
/* { dg-final { scan-assembler "\tmovz\t" } } */
/* { dg-final { scan-assembler "\tmovn\t" } } */
+/* { dg-final { scan-assembler "\tmovz\t" } } */
+/* { dg-final { scan-assembler "\tmovn\t" } } */
void ext_long (long);
@@ -17,3 +19,15 @@ sub5 (long i, long j, int k)
{
ext_long (!k ? i : j);
}
+
+NOMIPS16 long
+sub6 (int k)
+{
+ return !k ? 100 : 1000;
+}
+
+NOMIPS16 long
+sub7 (int k)
+{
+ return !k ? 100 : 1000;
+}