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Tue, 18 Jun 2024 01:03:39 -0700 (PDT) Received: from localhost.localdomain ([194.169.55.179]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c4c85a745bsm10163915a91.20.2024.06.18.01.03.38 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 18 Jun 2024 01:03:39 -0700 (PDT) From: YunQiang Su To: gcc-patches@gcc.gnu.org Cc: YunQiang Su Subject: [RFC] MIPS: Use SLL+BGEZ for one bit test on pre-R2 Date: Tue, 18 Jun 2024 16:03:31 +0800 Message-Id: <20240618080331.87938-1-syq@gcc.gnu.org> X-Mailer: git-send-email 2.39.3 (Apple Git-146) MIME-Version: 1.0 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, KAM_NUMSUBJECT, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org PR target/111376. Currently, we are using LUI/ANDI/BEQZ for on-bit-test if the bitpos>=16, while in fact we can use SLL/BGEZ. Note: 1) if bitpos<16, we can use ANDI/BEQZ. 2) For R2+, we have EXT. Known problems: 1. On some uarch, SLL has more delay, such as 74K: See the talk in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111376. 2. We haven't test it on any real pre-R2 hardware for performance. So, I request some test here. --- gcc/config/mips/mips.md | 33 +++++++++++ .../gcc.target/mips/mips3-one-bit-test.c | 55 +++++++++++++++++++ 2 files changed, 88 insertions(+) create mode 100644 gcc/testsuite/gcc.target/mips/mips3-one-bit-test.c diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 806fd29cf97..508fb1afa6c 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -6256,6 +6256,39 @@ (define_insn "*branch_bit_inverted" } [(set_attr "type" "branch") (set_attr "branch_likely" "no")]) + +(define_insn_and_split "*branch_on_bit" + [(set (pc) + (if_then_else + (match_operator 0 "equality_operator" + [(zero_extract:GPR (match_operand:GPR 2 "register_operand" "d") + (const_int 1) + (match_operand:GPR 3 "const_int_operand")) + (const_int 0)]) + (label_ref (match_operand 1)) + (pc)))] + "!ISA_HAS_BBIT && !ISA_HAS_EXT_INS && !TARGET_MIPS16 && UINTVAL (operands[3]) >= 16" + "#" + "&& !reload_completed" + [(set (match_dup 4) + (ashift:GPR (match_dup 2) (match_dup 3))) + (set (pc) + (if_then_else + (match_op_dup 0 [(match_dup 4) (const_int 0)]) + (label_ref (match_operand 1)) + (pc)))] +{ + int shift = GET_MODE_BITSIZE (mode) - 1 - INTVAL (operands[3]); + operands[3] = GEN_INT (shift); + operands[4] = gen_reg_rtx (mode); + + if (GET_CODE (operands[0]) == EQ) + operands[0] = gen_rtx_GE (mode, operands[4], const0_rtx); + else + operands[0] = gen_rtx_LT (mode, operands[4], const0_rtx); +} +[(set_attr "type" "branch")]) + ;; ;; .................... diff --git a/gcc/testsuite/gcc.target/mips/mips3-one-bit-test.c b/gcc/testsuite/gcc.target/mips/mips3-one-bit-test.c new file mode 100644 index 00000000000..50672e71d73 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/mips3-one-bit-test.c @@ -0,0 +1,55 @@ +/* { dg-options "-mips3 -mgp64" } */ +/* FIXME: -Os fails due to rtx_cost: PR115473. */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" "-Os" } { "" } } */ +/* { dg-final { scan-assembler "f32_15:.*andi\t\\\$4,\\\$4,0x8000" } } */ +/* { dg-final { scan-assembler "f32:.*sll\t\\\$4,\\\$4,15" } } */ +/* { dg-final { scan-assembler "f64_15:.*andi\t\\\$4,\\\$4,0x8000" } } */ +/* { dg-final { scan-assembler "f64:.*dsll\t\\\$4,\\\$4,47" } } */ + +/* Test to make sure we can use sll+bgtz to test one bit. + See PR111376. */ + +int f1(); +int f2(); + +/* If the bits is < 16, we can use andi+beqz. */ +NOMIPS16 int +f32_15(int a) +{ + int p = (a & (1<<15)); + if (p) + return f1(); + else + return f2(); +} + +/* If the bits >= 16, we can use sll+bgez. */ +NOMIPS16 int +f32(int a) +{ + int p = (a & (1<<16)); + if (p) + return f1(); + else + return f2(); +} + +NOMIPS16 int +f64_15(long long a) +{ + long long p = (a & (1LL<<15)); + if (p) + return f1(); + else + return f2(); +} + +NOMIPS16 int +f64(long long a) +{ + long long p = (a & (1LL<<16)); + if (p) + return f1(); + else + return f2(); +}