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Mon, 17 Jun 2024 11:33:32 -0700 (PDT) Received: from ewlu.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f855ee6eebsm82371835ad.158.2024.06.17.11.33.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jun 2024 11:33:31 -0700 (PDT) From: Edwin Lu To: gcc-patches@gcc.gnu.org Cc: gnu-toolchain@rivosinc.com, Edwin Lu , Robin Dapp Subject: [PATCH V3 2/2] RISC-V: Move mode assertion out of conditional branch in emit_insn Date: Mon, 17 Jun 2024 11:33:17 -0700 Message-Id: <20240617183317.2656046-3-ewlu@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240617183317.2656046-1-ewlu@rivosinc.com> References: <20240617183317.2656046-1-ewlu@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org When emitting insns, we have an early assertion to ensure the input operand's mode and the expanded operand's mode are the same; however, it does not perform this check if the pattern does not have an explicit machine mode specifying the operand. In this scenario, it will always assume that mode = Pmode to correctly satisfy the maybe_legitimize_operand check, however, there may be problems when working in 32 bit environments. Make the assert unconditional and replace it with an internal error for more descriptive logging gcc/ChangeLog: * config/riscv/riscv-v.cc: Move assert out of conditional block Signed-off-by: Edwin Lu Co-authored-by: Robin Dapp --- V2: change assert to internal error V3: No change --- gcc/config/riscv/riscv-v.cc | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 8911f5783c8..5306711c1b7 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -50,6 +50,7 @@ #include "rtx-vector-builder.h" #include "targhooks.h" #include "predict.h" +#include "errors.h" using namespace riscv_vector; @@ -290,11 +291,17 @@ public: always Pmode. */ if (mode == VOIDmode) mode = Pmode; - else - /* Early assertion ensures same mode since maybe_legitimize_operand - will check this. */ - gcc_assert (GET_MODE (ops[opno]) == VOIDmode - || GET_MODE (ops[opno]) == mode); + + /* Early assertion ensures same mode since maybe_legitimize_operand + will check this. */ + machine_mode required_mode = GET_MODE (ops[opno]); + if (required_mode != VOIDmode && required_mode != mode) + internal_error ("expected mode %s for operand %d of " + "insn %s but got mode %s.\n", + GET_MODE_NAME (mode), + opno, + insn_data[(int) icode].name, + GET_MODE_NAME (required_mode)); add_input_operand (ops[opno], mode); } @@ -346,7 +353,13 @@ public: else if (m_insn_flags & VXRM_RDN_P) add_rounding_mode_operand (VXRM_RDN); - gcc_assert (insn_data[(int) icode].n_operands == m_opno); + + if (insn_data[(int) icode].n_operands != m_opno) + internal_error ("invalid number of operands for insn %s, " + "expected %d but got %d.\n", + insn_data[(int) icode].name, + insn_data[(int) icode].n_operands, m_opno); + expand (icode, any_mem_p); }