From patchwork Mon Jun 17 09:53:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 1948589 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4W2lcG4bSdz20KL for ; Mon, 17 Jun 2024 19:55:10 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E80B8388204E for ; Mon, 17 Jun 2024 09:55:08 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id F2132385828E for ; Mon, 17 Jun 2024 09:54:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org F2132385828E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org F2132385828E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1718618055; cv=none; b=R1Cf+pNmc8f2AUkKCnMmLSNuuHiavDaqUKurFRMAaHSbtl2AVlGjME5mCuhJmaoKOH0IpFZ8htinU85yjsQzlmQSPBFiLuHInFfCo+uwe4T6Up+NvyfQLyeL23qR6Qpe677SAlJ0Y2dgwyNsKjudMIum5ohdTTThU+A3g7pw+l8= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1718618055; c=relaxed/simple; bh=E/aLIP4YVPKBv4wf1r2IulLIuBngaQzrR9HCtfTF2+g=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=Ks1L/hPEPj8+2yoIhGKgqzaOg4GoH+0W+mWxeC1EUsecgrwQKATInnpUHxbV3qzXt9AZZNbH1JqCW3mkwVuKsVQm0061A3gN0QE32+QDvZVdOS8nmkaqc0EJ5UFxr1hRgf+jge81kbP1vuW8wWX1GP3z8Mpa+5ZfwOBN6iiOpts= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 72A8FFEC; Mon, 17 Jun 2024 02:54:37 -0700 (PDT) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 496333F6A8; Mon, 17 Jun 2024 02:54:12 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Cc: Richard Sandiford Subject: [PATCH 5/8] aarch64: Add some uses of force_lowpart_subreg Date: Mon, 17 Jun 2024 10:53:33 +0100 Message-Id: <20240617095336.871176-6-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240617095336.871176-1-richard.sandiford@arm.com> References: <20240617095336.871176-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-20.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org This patch makes more use of force_lowpart_subreg, similarly to the recent patch for force_subreg. The criteria were: (1) The code is obviously specific to expand (where new pseudos can be created). (2) The value is obviously an rvalue rather than an lvalue. gcc/ PR target/115464 * config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin) (aarch64_expand_rwsr_builtin): Use force_lowpart_subreg instead of simplify_gen_subreg and lowpart_subreg. * config/aarch64/aarch64-sve-builtins-base.cc (svset_neonq_impl::expand): Likewise. * config/aarch64/aarch64-sve-builtins-sme.cc (add_load_store_slice_operand): Likewise. * config/aarch64/aarch64.cc (aarch64_sve_reinterpret): Likewise. (aarch64_addti_scratch_regs, aarch64_subvti_scratch_regs): Likewise. gcc/testsuite/ PR target/115464 * gcc.target/aarch64/sve/acle/general/pr115464_2.c: New test. --- gcc/config/aarch64/aarch64-builtins.cc | 11 +++++------ gcc/config/aarch64/aarch64-sve-builtins-base.cc | 2 +- gcc/config/aarch64/aarch64-sve-builtins-sme.cc | 2 +- gcc/config/aarch64/aarch64.cc | 14 +++++--------- .../aarch64/sve/acle/general/pr115464_2.c | 11 +++++++++++ 5 files changed, 23 insertions(+), 17 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc index 7d827cbc2ac..30669f8aa18 100644 --- a/gcc/config/aarch64/aarch64-builtins.cc +++ b/gcc/config/aarch64/aarch64-builtins.cc @@ -2579,8 +2579,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode) int lane = INTVAL (lane_idx); if (lane < nunits / 4) - op2 = simplify_gen_subreg (d->mode, op2, quadmode, - subreg_lowpart_offset (d->mode, quadmode)); + op2 = force_lowpart_subreg (d->mode, op2, quadmode); else { /* Select the upper 64 bits, either a V2SF or V4HF, this however @@ -2590,8 +2589,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode) gen_highpart_mode generates code that isn't optimal. */ rtx temp1 = gen_reg_rtx (d->mode); rtx temp2 = gen_reg_rtx (DImode); - temp1 = simplify_gen_subreg (d->mode, op2, quadmode, - subreg_lowpart_offset (d->mode, quadmode)); + temp1 = force_lowpart_subreg (d->mode, op2, quadmode); temp1 = force_subreg (V2DImode, temp1, d->mode, 0); if (BYTES_BIG_ENDIAN) emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx)); @@ -2836,7 +2834,7 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode) case AARCH64_WSR64: case AARCH64_WSRF64: case AARCH64_WSR128: - subreg = lowpart_subreg (sysreg_mode, input_val, mode); + subreg = force_lowpart_subreg (sysreg_mode, input_val, mode); break; case AARCH64_WSRF: subreg = gen_lowpart_SUBREG (SImode, input_val); @@ -2871,7 +2869,8 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode) case AARCH64_RSR64: case AARCH64_RSRF64: case AARCH64_RSR128: - return lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)), target, sysreg_mode); + return force_lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)), + target, sysreg_mode); case AARCH64_RSRF: subreg = gen_lowpart_SUBREG (SImode, target); return gen_lowpart_SUBREG (SFmode, subreg); diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc index 99932037124..aa26370d397 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc +++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc @@ -1183,7 +1183,7 @@ public: if (BYTES_BIG_ENDIAN) return e.use_exact_insn (code_for_aarch64_sve_set_neonq (mode)); insn_code icode = code_for_vcond_mask (mode, mode); - e.args[1] = lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1])); + e.args[1] = force_lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1])); e.add_output_operand (icode); e.add_input_operand (icode, e.args[1]); e.add_input_operand (icode, e.args[0]); diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc index f4c91bcbb95..b66b35ae60b 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc +++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc @@ -112,7 +112,7 @@ add_load_store_slice_operand (function_expander &e, insn_code icode, rtx base = e.args[argno]; if (e.mode_suffix_id == MODE_vnum) { - rtx vnum = lowpart_subreg (SImode, e.args[vnum_argno], DImode); + rtx vnum = force_lowpart_subreg (SImode, e.args[vnum_argno], DImode); base = simplify_gen_binary (PLUS, SImode, base, vnum); } e.add_input_operand (icode, base); diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 149e5b2f69a..c952a7cdefe 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -3288,7 +3288,7 @@ aarch64_sve_reinterpret (machine_mode mode, rtx x) /* can_change_mode_class must only return true if subregs and svreinterprets have the same semantics. */ if (targetm.can_change_mode_class (GET_MODE (x), mode, FP_REGS)) - return lowpart_subreg (mode, x, GET_MODE (x)); + return force_lowpart_subreg (mode, x, GET_MODE (x)); rtx res = gen_reg_rtx (mode); x = force_reg (GET_MODE (x), x); @@ -26870,9 +26870,8 @@ aarch64_addti_scratch_regs (rtx op1, rtx op2, rtx *low_dest, rtx *high_in2) { *low_dest = gen_reg_rtx (DImode); - *low_in1 = gen_lowpart (DImode, op1); - *low_in2 = simplify_gen_subreg (DImode, op2, TImode, - subreg_lowpart_offset (DImode, TImode)); + *low_in1 = force_lowpart_subreg (DImode, op1, TImode); + *low_in2 = force_lowpart_subreg (DImode, op2, TImode); *high_dest = gen_reg_rtx (DImode); *high_in1 = gen_highpart (DImode, op1); *high_in2 = simplify_gen_subreg (DImode, op2, TImode, @@ -26904,11 +26903,8 @@ aarch64_subvti_scratch_regs (rtx op1, rtx op2, rtx *low_dest, rtx *high_in2) { *low_dest = gen_reg_rtx (DImode); - *low_in1 = simplify_gen_subreg (DImode, op1, TImode, - subreg_lowpart_offset (DImode, TImode)); - - *low_in2 = simplify_gen_subreg (DImode, op2, TImode, - subreg_lowpart_offset (DImode, TImode)); + *low_in1 = force_lowpart_subreg (DImode, op1, TImode); + *low_in2 = force_lowpart_subreg (DImode, op2, TImode); *high_dest = gen_reg_rtx (DImode); *high_in1 = simplify_gen_subreg (DImode, op1, TImode, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c new file mode 100644 index 00000000000..f561c34f732 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c @@ -0,0 +1,11 @@ +/* { dg-options "-O2" } */ + +#include +#include +#include + +svuint16_t +convolve4_4_x (uint16x8x2_t permute_tbl, svuint16_t a) +{ + return svset_neonq_u16 (a, permute_tbl.val[1]); +}