From patchwork Mon Jun 17 09:53:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 1948588 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4W2lc90FZRz20KL for ; Mon, 17 Jun 2024 19:55:05 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5C74F3861877 for ; Mon, 17 Jun 2024 09:55:01 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 707403858C50 for ; Mon, 17 Jun 2024 09:54:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 707403858C50 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 707403858C50 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1718618053; cv=none; b=EbkDT2eXPTD2dwosS+YjWscff4GoGIBpiB59fsXwZm0S+OnzETyZ3jYSMAPoKgO1UgcSHahIyOuuh/p0tu4VD3tJC6Cja5KUWVa5j2bd1qThvZj4RXZU7uUe0XLyk86A3Tt2KVIVjFflda8BcZ7/98BrstqtviUaWLlxBTsOYbA= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1718618053; c=relaxed/simple; bh=A/HcW4OGqiiivDZJOXsqPwB16JhlfFzTqYeNHn+pPIw=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=Evh4z8Qfnl9e9a1KM6xjjiViLSNAzNH/WJrDQgpptMJ8FldaAotBGlc3pESo4VK6TWnSJcHqu5fw8BYrOx16GoUK5Dif6mCO/gJHHtXvRdFa7WLz+gB5fMz9p2o0ASKt3avSwQ/VDVQSQfSZv1GESmQqwL/pRPSmZ3PemA5NKu4= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D9296DA7; Mon, 17 Jun 2024 02:54:35 -0700 (PDT) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id AF88A3F6A8; Mon, 17 Jun 2024 02:54:10 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Cc: Richard Sandiford Subject: [PATCH 3/8] Make more use of force_subreg Date: Mon, 17 Jun 2024 10:53:31 +0100 Message-Id: <20240617095336.871176-4-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240617095336.871176-1-richard.sandiford@arm.com> References: <20240617095336.871176-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-20.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org This patch makes target-independent code use force_subreg instead of simplify_gen_subreg in some places. The criteria were: (1) The code is obviously specific to expand (where new pseudos can be created), or at least would be invalid to call when !can_create_pseudo_p () and temporaries are needed. (2) The value is obviously an rvalue rather than an lvalue. (3) The offset wasn't a simple lowpart or highpart calculation; a later patch will deal with those. Doing this should reduce the likelihood of bugs like PR115464 occuring in other situations. gcc/ * expmed.cc (store_bit_field_using_insv): Use force_subreg instead of simplify_gen_subreg. (store_bit_field_1): Likewise. (extract_bit_field_as_subreg): Likewise. (extract_integral_bit_field): Likewise. (emit_store_flag_1): Likewise. * expr.cc (convert_move): Likewise. (convert_modes): Likewise. (emit_group_load_1): Likewise. (emit_group_store): Likewise. (expand_assignment): Likewise. --- gcc/expmed.cc | 22 ++++++++-------------- gcc/expr.cc | 27 ++++++++++++--------------- 2 files changed, 20 insertions(+), 29 deletions(-) diff --git a/gcc/expmed.cc b/gcc/expmed.cc index 9ba01695f53..1f68e7be721 100644 --- a/gcc/expmed.cc +++ b/gcc/expmed.cc @@ -695,13 +695,7 @@ store_bit_field_using_insv (const extraction_insn *insv, rtx op0, if we must narrow it, be sure we do it correctly. */ if (GET_MODE_SIZE (value_mode) < GET_MODE_SIZE (op_mode)) - { - tmp = simplify_subreg (op_mode, value1, value_mode, 0); - if (! tmp) - tmp = simplify_gen_subreg (op_mode, - force_reg (value_mode, value1), - value_mode, 0); - } + tmp = force_subreg (op_mode, value1, value_mode, 0); else { if (targetm.mode_rep_extended (op_mode, value_mode) != UNKNOWN) @@ -806,7 +800,7 @@ store_bit_field_1 (rtx str_rtx, poly_uint64 bitsize, poly_uint64 bitnum, if (known_eq (bitnum, 0U) && known_eq (bitsize, GET_MODE_BITSIZE (GET_MODE (op0)))) { - sub = simplify_gen_subreg (GET_MODE (op0), value, fieldmode, 0); + sub = force_subreg (GET_MODE (op0), value, fieldmode, 0); if (sub) { if (reverse) @@ -1633,7 +1627,7 @@ extract_bit_field_as_subreg (machine_mode mode, rtx op0, && known_eq (bitsize, GET_MODE_BITSIZE (mode)) && lowpart_bit_field_p (bitnum, bitsize, op0_mode) && TRULY_NOOP_TRUNCATION_MODES_P (mode, op0_mode)) - return simplify_gen_subreg (mode, op0, op0_mode, bytenum); + return force_subreg (mode, op0, op0_mode, bytenum); return NULL_RTX; } @@ -2000,11 +1994,11 @@ extract_integral_bit_field (rtx op0, opt_scalar_int_mode op0_mode, return convert_extracted_bit_field (target, mode, tmode, unsignedp); } /* If OP0 is a hard register, copy it to a pseudo before calling - simplify_gen_subreg. */ + force_subreg. */ if (REG_P (op0) && HARD_REGISTER_P (op0)) op0 = copy_to_reg (op0); - op0 = simplify_gen_subreg (word_mode, op0, op0_mode.require (), - bitnum / BITS_PER_WORD * UNITS_PER_WORD); + op0 = force_subreg (word_mode, op0, op0_mode.require (), + bitnum / BITS_PER_WORD * UNITS_PER_WORD); op0_mode = word_mode; bitnum %= BITS_PER_WORD; } @@ -5774,8 +5768,8 @@ emit_store_flag_1 (rtx target, enum rtx_code code, rtx op0, rtx op1, /* Do a logical OR or AND of the two words and compare the result. */ - op00 = simplify_gen_subreg (word_mode, op0, int_mode, 0); - op01 = simplify_gen_subreg (word_mode, op0, int_mode, UNITS_PER_WORD); + op00 = force_subreg (word_mode, op0, int_mode, 0); + op01 = force_subreg (word_mode, op0, int_mode, UNITS_PER_WORD); tem = expand_binop (word_mode, op1 == const0_rtx ? ior_optab : and_optab, op00, op01, NULL_RTX, unsignedp, diff --git a/gcc/expr.cc b/gcc/expr.cc index 9cecc1758f5..31a7346e33f 100644 --- a/gcc/expr.cc +++ b/gcc/expr.cc @@ -301,7 +301,7 @@ convert_move (rtx to, rtx from, int unsignedp) GET_MODE_BITSIZE (to_mode))); if (VECTOR_MODE_P (to_mode)) - from = simplify_gen_subreg (to_mode, from, GET_MODE (from), 0); + from = force_subreg (to_mode, from, GET_MODE (from), 0); else to = simplify_gen_subreg (from_mode, to, GET_MODE (to), 0); @@ -935,7 +935,7 @@ convert_modes (machine_mode mode, machine_mode oldmode, rtx x, int unsignedp) { gcc_assert (known_eq (GET_MODE_BITSIZE (mode), GET_MODE_BITSIZE (oldmode))); - return simplify_gen_subreg (mode, x, oldmode, 0); + return force_subreg (mode, x, oldmode, 0); } temp = gen_reg_rtx (mode); @@ -3072,8 +3072,8 @@ emit_group_load_1 (rtx *tmps, rtx dst, rtx orig_src, tree type, } } else if (CONSTANT_P (src) && GET_MODE (dst) != BLKmode - && XVECLEN (dst, 0) > 1) - tmps[i] = simplify_gen_subreg (mode, src, GET_MODE (dst), bytepos); + && XVECLEN (dst, 0) > 1) + tmps[i] = force_subreg (mode, src, GET_MODE (dst), bytepos); else if (CONSTANT_P (src)) { if (known_eq (bytelen, ssize)) @@ -3297,7 +3297,7 @@ emit_group_store (rtx orig_dst, rtx src, tree type ATTRIBUTE_UNUSED, if (known_eq (rtx_to_poly_int64 (XEXP (XVECEXP (src, 0, start), 1)), bytepos)) { - temp = simplify_gen_subreg (outer, tmps[start], inner, 0); + temp = force_subreg (outer, tmps[start], inner, 0); if (temp) { emit_move_insn (dst, temp); @@ -3317,7 +3317,7 @@ emit_group_store (rtx orig_dst, rtx src, tree type ATTRIBUTE_UNUSED, finish - 1), 1)), bytepos)) { - temp = simplify_gen_subreg (outer, tmps[finish - 1], inner, 0); + temp = force_subreg (outer, tmps[finish - 1], inner, 0); if (temp) { emit_move_insn (dst, temp); @@ -6191,11 +6191,9 @@ expand_assignment (tree to, tree from, bool nontemporal) to_mode = GET_MODE_INNER (to_mode); machine_mode from_mode = GET_MODE_INNER (GET_MODE (result)); rtx from_real - = simplify_gen_subreg (to_mode, XEXP (result, 0), - from_mode, 0); + = force_subreg (to_mode, XEXP (result, 0), from_mode, 0); rtx from_imag - = simplify_gen_subreg (to_mode, XEXP (result, 1), - from_mode, 0); + = force_subreg (to_mode, XEXP (result, 1), from_mode, 0); if (!from_real || !from_imag) goto concat_store_slow; emit_move_insn (XEXP (to_rtx, 0), from_real); @@ -6211,8 +6209,7 @@ expand_assignment (tree to, tree from, bool nontemporal) if (MEM_P (result)) from_rtx = change_address (result, to_mode, NULL_RTX); else - from_rtx - = simplify_gen_subreg (to_mode, result, from_mode, 0); + from_rtx = force_subreg (to_mode, result, from_mode, 0); if (from_rtx) { emit_move_insn (XEXP (to_rtx, 0), @@ -6224,10 +6221,10 @@ expand_assignment (tree to, tree from, bool nontemporal) { to_mode = GET_MODE_INNER (to_mode); rtx from_real - = simplify_gen_subreg (to_mode, result, from_mode, 0); + = force_subreg (to_mode, result, from_mode, 0); rtx from_imag - = simplify_gen_subreg (to_mode, result, from_mode, - GET_MODE_SIZE (to_mode)); + = force_subreg (to_mode, result, from_mode, + GET_MODE_SIZE (to_mode)); if (!from_real || !from_imag) goto concat_store_slow; emit_move_insn (XEXP (to_rtx, 0), from_real);