From patchwork Mon Jun 17 09:53:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 1948587 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4W2lbv2hHxz20KL for ; Mon, 17 Jun 2024 19:54:51 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9C3CC3857022 for ; Mon, 17 Jun 2024 09:54:49 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id AAED93858C48 for ; Mon, 17 Jun 2024 09:54:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org AAED93858C48 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org AAED93858C48 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1718618052; cv=none; b=VFojcoUjdhs8ySpNrXrpPEZY5c5tKdiHHLnU9Rj5G/y8uIRKPeLSiQYie4izoSEVzvVkEkRJjebEzpsgfgkXZpnllBczxI3wjmZacQ09QOrH022P1D8lbaDVw2fGo3lJXcSZO5i5enBtx6ZXLebWivQq6GAfBQ+lyMMQvZUHwj4= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1718618052; c=relaxed/simple; bh=bXL0+kTMjfNHd77NeJgNXqGZKGxiZKwz5cCFdUy7eFk=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=uMkTZy+8IW8N5u738i5cN3LcRpfso+a8G9jTeZLb1ZiyrFCUd+99ki1+tS5xxXQFe6FJ77Ea4310/DXfoRZBtq0l6yE2CXnlnhqkGFfyXJFsuUVhbZrQbzZ9EezzRSDv4qdHgBaCzSgMJhCmAsXvkXBpFBWm/q7Z56VqthQhKwI= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 17CA21516; Mon, 17 Jun 2024 02:54:35 -0700 (PDT) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E280F3F6A8; Mon, 17 Jun 2024 02:54:09 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Cc: Richard Sandiford Subject: [PATCH 2/8] aarch64: Use force_subreg in more places Date: Mon, 17 Jun 2024 10:53:30 +0100 Message-Id: <20240617095336.871176-3-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240617095336.871176-1-richard.sandiford@arm.com> References: <20240617095336.871176-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-20.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org This patch makes the aarch64 code use force_subreg instead of simplify_gen_subreg in more places. The criteria were: (1) The code is obviously specific to expand (where new pseudos can be created). (2) The value is obviously an rvalue rather than an lvalue. (3) The offset wasn't a simple lowpart or highpart calculation; a later patch will deal with those. gcc/ * config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin): Use force_subreg instead of simplify_gen_subreg. * config/aarch64/aarch64-simd.md (ctz2): Likewise. * config/aarch64/aarch64-sve-builtins-base.cc (svget_impl::expand): Likewise. (svget_neonq_impl::expand): Likewise. * config/aarch64/aarch64-sve-builtins-functions.h (multireg_permute::expand): Likewise. --- gcc/config/aarch64/aarch64-builtins.cc | 4 ++-- gcc/config/aarch64/aarch64-simd.md | 4 ++-- gcc/config/aarch64/aarch64-sve-builtins-base.cc | 8 +++----- gcc/config/aarch64/aarch64-sve-builtins-functions.h | 6 +++--- 4 files changed, 10 insertions(+), 12 deletions(-) diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc index d589e59defc..7d827cbc2ac 100644 --- a/gcc/config/aarch64/aarch64-builtins.cc +++ b/gcc/config/aarch64/aarch64-builtins.cc @@ -2592,12 +2592,12 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode) rtx temp2 = gen_reg_rtx (DImode); temp1 = simplify_gen_subreg (d->mode, op2, quadmode, subreg_lowpart_offset (d->mode, quadmode)); - temp1 = simplify_gen_subreg (V2DImode, temp1, d->mode, 0); + temp1 = force_subreg (V2DImode, temp1, d->mode, 0); if (BYTES_BIG_ENDIAN) emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx)); else emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const1_rtx)); - op2 = simplify_gen_subreg (d->mode, temp2, GET_MODE (temp2), 0); + op2 = force_subreg (d->mode, temp2, GET_MODE (temp2), 0); /* And recalculate the index. */ lane -= nunits / 4; diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 0bb39091a38..01b084d8ccb 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -389,8 +389,8 @@ (define_expand "ctz2" "TARGET_SIMD" { emit_insn (gen_bswap2 (operands[0], operands[1])); - rtx op0_castsi2qi = simplify_gen_subreg(mode, operands[0], - mode, 0); + rtx op0_castsi2qi = force_subreg (mode, operands[0], + mode, 0); emit_insn (gen_aarch64_rbit (op0_castsi2qi, op0_castsi2qi)); emit_insn (gen_clz2 (operands[0], operands[0])); DONE; diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc index 823d60040f9..99932037124 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc +++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc @@ -1121,9 +1121,8 @@ public: expand (function_expander &e) const override { /* Fold the access into a subreg rvalue. */ - return simplify_gen_subreg (e.vector_mode (0), e.args[0], - GET_MODE (e.args[0]), - INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR); + return force_subreg (e.vector_mode (0), e.args[0], GET_MODE (e.args[0]), + INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR); } }; @@ -1157,8 +1156,7 @@ public: e.add_fixed_operand (indices); return e.generate_insn (icode); } - return simplify_gen_subreg (e.result_mode (), e.args[0], - GET_MODE (e.args[0]), 0); + return force_subreg (e.result_mode (), e.args[0], GET_MODE (e.args[0]), 0); } }; diff --git a/gcc/config/aarch64/aarch64-sve-builtins-functions.h b/gcc/config/aarch64/aarch64-sve-builtins-functions.h index 3b8e575e98e..7d06a57ff83 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-functions.h +++ b/gcc/config/aarch64/aarch64-sve-builtins-functions.h @@ -639,9 +639,9 @@ public: { machine_mode elt_mode = e.vector_mode (0); rtx arg = e.args[0]; - e.args[0] = simplify_gen_subreg (elt_mode, arg, GET_MODE (arg), 0); - e.args.safe_push (simplify_gen_subreg (elt_mode, arg, GET_MODE (arg), - GET_MODE_SIZE (elt_mode))); + e.args[0] = force_subreg (elt_mode, arg, GET_MODE (arg), 0); + e.args.safe_push (force_subreg (elt_mode, arg, GET_MODE (arg), + GET_MODE_SIZE (elt_mode))); } return e.use_exact_insn (icode); }