@@ -2592,12 +2592,12 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
rtx temp2 = gen_reg_rtx (DImode);
temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
subreg_lowpart_offset (d->mode, quadmode));
- temp1 = simplify_gen_subreg (V2DImode, temp1, d->mode, 0);
+ temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
if (BYTES_BIG_ENDIAN)
emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
else
emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const1_rtx));
- op2 = simplify_gen_subreg (d->mode, temp2, GET_MODE (temp2), 0);
+ op2 = force_subreg (d->mode, temp2, GET_MODE (temp2), 0);
/* And recalculate the index. */
lane -= nunits / 4;
@@ -389,8 +389,8 @@ (define_expand "ctz<mode>2"
"TARGET_SIMD"
{
emit_insn (gen_bswap<mode>2 (operands[0], operands[1]));
- rtx op0_castsi2qi = simplify_gen_subreg(<VS:VSI2QI>mode, operands[0],
- <MODE>mode, 0);
+ rtx op0_castsi2qi = force_subreg (<VS:VSI2QI>mode, operands[0],
+ <MODE>mode, 0);
emit_insn (gen_aarch64_rbit<VS:vsi2qi> (op0_castsi2qi, op0_castsi2qi));
emit_insn (gen_clz<mode>2 (operands[0], operands[0]));
DONE;
@@ -1121,9 +1121,8 @@ public:
expand (function_expander &e) const override
{
/* Fold the access into a subreg rvalue. */
- return simplify_gen_subreg (e.vector_mode (0), e.args[0],
- GET_MODE (e.args[0]),
- INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
+ return force_subreg (e.vector_mode (0), e.args[0], GET_MODE (e.args[0]),
+ INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
}
};
@@ -1157,8 +1156,7 @@ public:
e.add_fixed_operand (indices);
return e.generate_insn (icode);
}
- return simplify_gen_subreg (e.result_mode (), e.args[0],
- GET_MODE (e.args[0]), 0);
+ return force_subreg (e.result_mode (), e.args[0], GET_MODE (e.args[0]), 0);
}
};
@@ -639,9 +639,9 @@ public:
{
machine_mode elt_mode = e.vector_mode (0);
rtx arg = e.args[0];
- e.args[0] = simplify_gen_subreg (elt_mode, arg, GET_MODE (arg), 0);
- e.args.safe_push (simplify_gen_subreg (elt_mode, arg, GET_MODE (arg),
- GET_MODE_SIZE (elt_mode)));
+ e.args[0] = force_subreg (elt_mode, arg, GET_MODE (arg), 0);
+ e.args.safe_push (force_subreg (elt_mode, arg, GET_MODE (arg),
+ GET_MODE_SIZE (elt_mode)));
}
return e.use_exact_insn (icode);
}
This patch makes the aarch64 code use force_subreg instead of simplify_gen_subreg in more places. The criteria were: (1) The code is obviously specific to expand (where new pseudos can be created). (2) The value is obviously an rvalue rather than an lvalue. (3) The offset wasn't a simple lowpart or highpart calculation; a later patch will deal with those. gcc/ * config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin): Use force_subreg instead of simplify_gen_subreg. * config/aarch64/aarch64-simd.md (ctz<mode>2): Likewise. * config/aarch64/aarch64-sve-builtins-base.cc (svget_impl::expand): Likewise. (svget_neonq_impl::expand): Likewise. * config/aarch64/aarch64-sve-builtins-functions.h (multireg_permute::expand): Likewise. --- gcc/config/aarch64/aarch64-builtins.cc | 4 ++-- gcc/config/aarch64/aarch64-simd.md | 4 ++-- gcc/config/aarch64/aarch64-sve-builtins-base.cc | 8 +++----- gcc/config/aarch64/aarch64-sve-builtins-functions.h | 6 +++--- 4 files changed, 10 insertions(+), 12 deletions(-)