From patchwork Fri Jun 14 02:13:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1947624 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=Yo9TVwfZ; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4W0jWm1wltz20XL for ; Fri, 14 Jun 2024 12:14:12 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 80850388264E for ; Fri, 14 Jun 2024 02:14:09 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by sourceware.org (Postfix) with ESMTPS id 1F099388206F for ; Fri, 14 Jun 2024 02:13:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1F099388206F Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 1F099388206F Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1718331218; cv=none; b=DdevZFfJL6ZTxp/Q39aRrQD1OL4IR0mU6o+V5s/D/RRJc6cDSyYlfHslDoWdcFFNu/a7s7mSXlW7AD9skb8TyvsRYfOVK/QhpCEuUMEp+qQs6TspHYuw5fY9tC7fPkyWYW2BfcJit7QrEIU8Ut17rGNiz1HAhA76YmHnjLYIycY= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1718331218; c=relaxed/simple; bh=ISGQ6/9rqcJPiR4TIUAvMuaihyXad2Rf2aRZdLLWQV8=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=F2TZnp70TT7TONJUL7e9x6Kp183B0f8U//84CTNL6fY6ZeoNsOer+vtnZmlTpmOGdSt35UqXJszB2Isw/n78wpyIdvRwS69oC+rRRDxfp7/08WVJaUq5uK+DiGU9zAPpRgYUWJEHqBRT5s2dLzOr9ATT/qqi1uClVDkNMIKcMFM= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718331215; x=1749867215; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=ISGQ6/9rqcJPiR4TIUAvMuaihyXad2Rf2aRZdLLWQV8=; b=Yo9TVwfZAsE94odq2jvZm1af2Zo4DJKn6Zqu1mB3npvfhOcrWJybCt9v n/SPuOYmfB/iyyYMtN9cDbHhTbEAyjw9TAoZUZY5wQgG6XhP+eLG2NbiM uDHVsdDRkAURaKhy9vGSA5UprAOf20Bd0oMX/JrHMV1n7zhKXwqq37/1Z +Jiat9/Z3/azoaq9VE1DIbFJIuM85b2CZVZ4tb//FOw48gvnzLw+FYe2N PMm6jJXmRTViISCDoralDefHvadceH3+SqK/8Ux4C0KjDMeUjrTySsxRN haNZjWih2zSrqSWam2Aj4PunY8Xm3CXovGxJEy5Bx1ehERFXrbC8Fg+77 A==; X-CSE-ConnectionGUID: PfhyN5nQSiCaSNb2tdWE9A== X-CSE-MsgGUID: Wutb1/IUS/+z1OfPXZQ5QQ== X-IronPort-AV: E=McAfee;i="6700,10204,11102"; a="15431430" X-IronPort-AV: E=Sophos;i="6.08,236,1712646000"; d="scan'208";a="15431430" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jun 2024 19:13:34 -0700 X-CSE-ConnectionGUID: znksETsXRBy9Fp+3IVClIQ== X-CSE-MsgGUID: plgOfyeoSoilFNz4g9Ad+Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,236,1712646000"; d="scan'208";a="45481301" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orviesa004.jf.intel.com with ESMTP; 13 Jun 2024 19:13:31 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 00CAF1007014; Fri, 14 Jun 2024 10:13:29 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v1 1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3 Date: Fri, 14 Jun 2024 10:13:21 +0800 Message-Id: <20240614021328.3032144-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_LOTSOFHASH, KAM_NUMSUBJECT, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li After the middle-end support the form 3 of unsigned SAT_SUB and the RISC-V backend implement the scalar .SAT_SUB, add more test case to cover the form 3 of unsigned .SAT_SUB. Form 3: #define SAT_SUB_U_3(T) \ T sat_sub_u_3_##T (T x, T y) \ { \ return x > y ? x - y : 0; \ } Passed the rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_arith.h: Add helper macro for test. * gcc.target/riscv/sat_u_sub-10.c: New test. * gcc.target/riscv/sat_u_sub-11.c: New test. * gcc.target/riscv/sat_u_sub-12.c: New test. * gcc.target/riscv/sat_u_sub-9.c: New test. * gcc.target/riscv/sat_u_sub-run-10.c: New test. * gcc.target/riscv/sat_u_sub-run-11.c: New test. * gcc.target/riscv/sat_u_sub-run-12.c: New test. * gcc.target/riscv/sat_u_sub-run-9.c: New test. Signed-off-by: Pan Li Signed-off-by: Pan Li --- gcc/testsuite/gcc.target/riscv/sat_arith.h | 8 ++++++ gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c | 19 ++++++++++++++ gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c | 18 +++++++++++++ gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c | 17 +++++++++++++ gcc/testsuite/gcc.target/riscv/sat_u_sub-9.c | 18 +++++++++++++ .../gcc.target/riscv/sat_u_sub-run-10.c | 25 +++++++++++++++++++ .../gcc.target/riscv/sat_u_sub-run-11.c | 25 +++++++++++++++++++ .../gcc.target/riscv/sat_u_sub-run-12.c | 25 +++++++++++++++++++ .../gcc.target/riscv/sat_u_sub-run-9.c | 25 +++++++++++++++++++ 9 files changed, 180 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-9.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-11.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-12.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-9.c diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h index bc9a372b6df..50c65cdea49 100644 --- a/gcc/testsuite/gcc.target/riscv/sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h @@ -92,8 +92,16 @@ sat_u_sub_##T##_fmt_2 (T x, T y) \ return (x - y) & (-(T)(x > y)); \ } +#define DEF_SAT_U_SUB_FMT_3(T) \ +T __attribute__((noinline)) \ +sat_u_sub_##T##_fmt_3 (T x, T y) \ +{ \ + return x > y ? x - y : 0; \ +} + #define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y) #define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y) +#define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y) #define DEF_VEC_SAT_U_SUB_FMT_1(T) \ void __attribute__((noinline)) \ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c new file mode 100644 index 00000000000..6e78164865f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_sub_uint16_t_fmt_3: +** sub\s+[atx][0-9]+,\s*a0,\s*a1 +** sltu\s+[atx][0-9]+,\s*a0,\s*a1 +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 +** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ +** slli\s+a0,\s*a0,\s*48 +** srli\s+a0,\s*a0,\s*48 +** ret +*/ +DEF_SAT_U_SUB_FMT_3(uint16_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c new file mode 100644 index 00000000000..84e34657f55 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_sub_uint32_t_fmt_3: +** sub\s+[atx][0-9]+,\s*a0,\s*a1 +** sltu\s+[atx][0-9]+,\s*a0,\s*a1 +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 +** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ +** sext.w\s+a0,\s*a0 +** ret +*/ +DEF_SAT_U_SUB_FMT_3(uint32_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c new file mode 100644 index 00000000000..eea282b21ae --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_sub_uint64_t_fmt_3: +** sub\s+[atx][0-9]+,\s*a0,\s*a1 +** sltu\s+[atx][0-9]+,\s*a0,\s*a1 +** addi\s+a0,\s*[atx][0-9]+,\s*-1 +** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ +** ret +*/ +DEF_SAT_U_SUB_FMT_3(uint64_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-9.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-9.c new file mode 100644 index 00000000000..b24bf3eb549 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-9.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_sub_uint8_t_fmt_3: +** sub\s+[atx][0-9]+,\s*a0,\s*a1 +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 +** and\s+a0,\s*a0,\s*[atx][0-9]+ +** andi\s+a0,\s*a0,\s*0xff +** ret +*/ +DEF_SAT_U_SUB_FMT_3(uint8_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-10.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-10.c new file mode 100644 index 00000000000..ea52ff4573e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-10.c @@ -0,0 +1,25 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint16_t +#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_3 + +DEF_SAT_U_SUB_FMT_3(T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 0, }, + { 1, 1, 0, }, + { 65535, 65534, 1, }, + { 65535, 65535, 0, }, + { 65534, 65535, 0, }, + { 65533, 65534, 0, }, + { 0, 65535, 0, }, + { 1, 65535, 0, }, + { 35, 5, 30, }, +}; + +#include "scalar_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-11.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-11.c new file mode 100644 index 00000000000..fdea8916ab3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-11.c @@ -0,0 +1,25 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint32_t +#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_3 + +DEF_SAT_U_SUB_FMT_3(T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 0, }, + { 1, 1, 0, }, + { 4294967295, 4294967294, 1, }, + { 4294967295, 4294967295, 0, }, + { 4294967294, 4294967295, 0, }, + { 4294967293, 4294967294, 0, }, + { 1, 4294967295, 0, }, + { 2, 4294967295, 0, }, + { 5, 1, 4, }, +}; + +#include "scalar_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-12.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-12.c new file mode 100644 index 00000000000..164ee77fb76 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-12.c @@ -0,0 +1,25 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint64_t +#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_3 + +DEF_SAT_U_SUB_FMT_3(T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 0, }, + { 1, 1, 0, }, + { 18446744073709551615u, 18446744073709551614u, 1, }, + { 18446744073709551615u, 18446744073709551615u, 0, }, + { 18446744073709551614u, 18446744073709551615u, 0, }, + { 18446744073709551613u, 18446744073709551614u, 0, }, + { 0, 18446744073709551615u, 0, }, + { 1, 18446744073709551615u, 0, }, + { 43, 11, 32, }, +}; + +#include "scalar_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-9.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-9.c new file mode 100644 index 00000000000..724adf92d3e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-9.c @@ -0,0 +1,25 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint8_t +#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_3 + +DEF_SAT_U_SUB_FMT_3(T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 0, }, + { 1, 1, 0, }, + { 255, 254, 1, }, + { 255, 255, 0, }, + { 254, 255, 0, }, + { 253, 254, 0, }, + { 0, 255, 0, }, + { 1, 255, 0, }, + { 32, 5, 27, }, +}; + +#include "scalar_sat_binary.h"