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Thu, 13 Jun 2024 02:19:46 GMT Received: from smtpav07.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E8F412004B; Thu, 13 Jun 2024 02:19:43 +0000 (GMT) Received: from smtpav07.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9AE0A20040; Thu, 13 Jun 2024 02:19:42 +0000 (GMT) Received: from nilram.aus.stglabs.ibm.com (unknown [9.40.204.36]) by smtpav07.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 13 Jun 2024 02:19:42 +0000 (GMT) From: Jiufu Guo To: gcc-patches@gcc.gnu.org Cc: segher@kernel.crashing.org, linkw@gcc.gnu.org, dje.gcc@gmail.com, bergner@linux.ibm.com, guojiufu@linux.ibm.com Subject: [PATCH V5 2/2] split complicate 64bit constant to memory for -m32 -mpowerpc64 Date: Thu, 13 Jun 2024 10:19:39 +0800 Message-ID: <20240613021940.4000707-2-guojiufu@linux.ibm.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240613021940.4000707-1-guojiufu@linux.ibm.com> References: <20240613021940.4000707-1-guojiufu@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: FDwOTxCsClfuIrakPPhf03taK1-dvMfu X-Proofpoint-GUID: Wlc4jpxpEAgYuwdLXQKA9kggjp7O814M X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-12_12,2024-06-12_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 adultscore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 mlxscore=0 phishscore=0 clxscore=1015 mlxlogscore=999 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2406130010 X-Spam-Status: No, score=-9.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, KAM_SHORT, KAM_STOCKGEN, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Hi, For "-m32 -mpowerpc64", it is also ok to use just one instruciton (p?ld) to loading 64bit constant from memory. So, splitting the complicate 64bit constant to constant pool should also work under this case. Compare with previous version, this update the threshold for the insn number of the constant. Bootstrap and regtest pass on ppc64{,le}. Also no regression for "-m32 -mpowerpc64" variation on ppc64. Is this ok for trunk? BR, Jeff(Jiufu) Guo gcc/ChangeLog: * config/rs6000/rs6000.cc (rs6000_emit_set_const): Split constant to pool for "-m32 -mpowerpc64". gcc/testsuite/ChangeLog: * gcc.target/powerpc/pr63281.c: Allow checking -m32. --- gcc/config/rs6000/rs6000.cc | 21 ++++++++++++++++++++- gcc/testsuite/gcc.target/powerpc/pr63281.c | 4 ++-- 2 files changed, 22 insertions(+), 3 deletions(-) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index bc9d6f5c34f..278b39ac9a3 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -10242,7 +10242,8 @@ rs6000_emit_set_const (rtx dest, rtx source) } else if ((can_create_pseudo_p () || base_reg_operand (dest, mode)) - && TARGET_64BIT && num_insns_constant (source, mode) > 2) + && num_insns_constant (source, mode) + > (TARGET_32BIT && TARGET_CMODEL != CMODEL_SMALL ? 3 : 2)) { rtx sym = force_const_mem (mode, source); if (TARGET_TOC && SYMBOL_REF_P (XEXP (sym, 0)) @@ -10252,6 +10253,24 @@ rs6000_emit_set_const (rtx dest, rtx source) sym = gen_const_mem (mode, toc); set_mem_alias_set (sym, get_TOC_alias_set ()); } + else if (TARGET_32BIT) + { + /* After RA, reuse 'DEST' reg. */ + rtx addr = can_create_pseudo_p () + ? gen_reg_rtx (Pmode) + : gen_rtx_REG (Pmode, REGNO (dest)); + rtx sym_ref = XEXP (sym, 0); + if (flag_pic) + emit_move_insn (addr, sym_ref); + else + { + emit_move_insn (addr, gen_rtx_HIGH (Pmode, sym_ref)); + emit_move_insn (addr, gen_rtx_LO_SUM (Pmode, addr, sym_ref)); + } + rtx mem = gen_rtx_MEM (mode, addr); + MEM_COPY_ATTRIBUTES (mem, sym); + sym = mem; + } emit_move_insn (dest, sym); } diff --git a/gcc/testsuite/gcc.target/powerpc/pr63281.c b/gcc/testsuite/gcc.target/powerpc/pr63281.c index 9763a7181fc..d3d620d3bee 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr63281.c +++ b/gcc/testsuite/gcc.target/powerpc/pr63281.c @@ -1,4 +1,4 @@ -/* Check loading constant from memory pool. */ +/* Check loading constant from memory pool under -mpowerpc64 (include -m32). */ /* { dg-options "-O2 -mpowerpc64" } */ void @@ -7,5 +7,5 @@ foo (unsigned long long *a) *a++ = 0x2351847027482577ULL; } -/* { dg-final { scan-assembler-times {\mp?ld\M} 1 { target { lp64 } } } } */ +/* { dg-final { scan-assembler-times {\mp?ld\M} 1 { target { has_arch_ppc64 } } } } */