From patchwork Tue Jun 11 17:06:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 1946431 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.a=rsa-sha256 header.s=20230601 header.b=Al1Bid46; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4VzFTM0NjKz20Pb for ; Wed, 12 Jun 2024 03:07:03 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8A8F43861035 for ; Tue, 11 Jun 2024 17:07:00 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by sourceware.org (Postfix) with ESMTPS id 61F13385DDDC for ; Tue, 11 Jun 2024 17:06:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 61F13385DDDC Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 61F13385DDDC Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::62e ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1718125584; cv=none; b=qi0awvnITk/GE/lPvvNd4dL2cEhNzl85aqPkd+mTipHxovjXuRonBJ0SueWzHAOkwv0X+Oi8ux/8JHO03A5KVRHbi0BjJJ6TsOQqswpKnGYtQXxA3gan3/QbCanL4XcU0lwIo0JBtrW4m0hjR6csurhqkR+FoL3hpW0TUDtU1fU= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1718125584; c=relaxed/simple; bh=ennI9GWJFjssHDr5vgewDLdOa9vBZaVg5rVaMtCoVp4=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=Xz05dvFGasxnvvY/BMwhb0MiAYVmKUq+hQ62gthX1PNY2p/6KE1Rqywva0wmVKCB9X57mty77NGL+o3mQ9MjLB0gFeJUTDibsHFumiBKNZtF0occegYyN2IsVwLQ78e503wT/9q3HWr9PwsZH1NTe60tWJAVeBHDgwJ4fxE+Wos= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-1f4c7b022f8so54120765ad.1 for ; Tue, 11 Jun 2024 10:06:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1718125580; x=1718730380; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=Ajr3axwMIrdd1TBfGhogfLXN7epTLqx0FzmfnhBkLmE=; b=Al1Bid46jIUmtZ4kfndFTy0oPpShIzt1hPshI23yn8+QNMOWx9vbVYxWG86graDBsT qowlZgWKxrxhgL6d4mDocVWexAfCow1CepIknb38AQAcPVLrj90Fc6BERDia7KkGzOwX 4m2KABT00rv0AnkzA7G2b81T2MpawTNvP1N7GQjO61xKfKcfsbaMoGCamW6TRBYsBSI6 T5qap2IL0mGtbavwvFITwJBhsDGm5gaBtQjGl35ql1F2ZE9yd7I5I+nTRKPmsBG1QaWP LIQ83hTABRbDaNFWRZ0U/Nq1zjktcm7jhHf3ZWeR35QK6Qa4JFMpqosFjQFTPDCgv5fi NgYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718125580; x=1718730380; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=Ajr3axwMIrdd1TBfGhogfLXN7epTLqx0FzmfnhBkLmE=; b=RhK3vAZHq/tff9Yez6WDAgDRnRyINTXd88nj6gTHzwfU7XkOUte7UmqmtdUb5kLydH 8cKa2hbQ7CWxBgDu2Dz8wMSwkCUjrrHCnpxKFRBTEgn24WtwCg5Z8iGe4E7gg98a+w2h xOpOpp92RvAgB8nuDnvAHGqh7VwCqF2SkpHyAvHGQ0CiZYQnpqa894Ch2YkqMkd7Gvk9 D08ZgdVfYPHvn2TTbv6/8nIirlxwVMqLyBJ9Q/QCuIuvDbvskzq/+JgoK1vC0SON82Hb HdueC2NkQw+V01183ET/CsXj4VJA08ne2s9S/51AGR6nzuQRpy4iVSzm2fsjhPlEX4i9 a4ZQ== X-Gm-Message-State: AOJu0YwvnEKJFKzVMA9Zbtgayw2XGNvFZByQXSFPkMCXtmkxiWZ8X3zv IoseDmpOB2+ulztK55Ha53ZMmJI53P9SNMorsXj3+6qSJmoFjp6p9s5th6e1of6I4vgNDKop2Oy H X-Google-Smtp-Source: AGHT+IGhyEbiHe5aMZT/D3sDsgC9opHdHBn8uqHDrUv2sJySqGEx9ajbrftaeqWdWn3n0YwIfMGM0w== X-Received: by 2002:a17:902:dad1:b0:1f7:2477:aeaa with SMTP id d9443c01a7336-1f72477b1afmr51722805ad.41.1718125579511; Tue, 11 Jun 2024 10:06:19 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.145.13.30]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f72d450697sm18363035ad.168.2024.06.11.10.06.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jun 2024 10:06:19 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: Edwin Lu , Patrick O'Neill Subject: [Committed 1/3] RISC-V: Add basic Zaamo and Zalrsc support Date: Tue, 11 Jun 2024 10:06:03 -0700 Message-ID: <20240611170605.2376245-1-patrick@rivosinc.com> X-Mailer: git-send-email 2.43.2 MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Edwin Lu There is a proposal to split the A extension into two parts: Zaamo and Zalrsc. This patch adds basic support by making the A extension imply Zaamo and Zalrsc. Proposal: https://github.com/riscv/riscv-zaamo-zalrsc/tags gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add Zaamo and Zalrsc. * config/riscv/arch-canonicalize: Make A imply Zaamo and Zalrsc. * config/riscv/riscv.opt: Add Zaamo and Zalrsc * config/riscv/sync.md: Convert TARGET_ATOMIC to TARGET_ZAAMO and TARGET_ZALRSC. gcc/testsuite/ChangeLog: * gcc.target/riscv/attribute-15.c: Adjust expected arch string. * gcc.target/riscv/attribute-16.c: Ditto. * gcc.target/riscv/attribute-17.c: Ditto. * gcc.target/riscv/attribute-18.c: Ditto. * gcc.target/riscv/pr110696.c: Ditto. * gcc.target/riscv/rvv/base/pr114352-1.c: Ditto. * gcc.target/riscv/rvv/base/pr114352-3.c: Ditto. Signed-off-by: Edwin Lu Co-authored-by: Patrick O'Neill --- gcc/common/config/riscv/riscv-common.cc | 11 +++++-- gcc/config/riscv/arch-canonicalize | 1 + gcc/config/riscv/riscv.opt | 6 +++- gcc/config/riscv/sync.md | 30 +++++++++---------- gcc/testsuite/gcc.target/riscv/attribute-15.c | 2 +- gcc/testsuite/gcc.target/riscv/attribute-16.c | 2 +- gcc/testsuite/gcc.target/riscv/attribute-17.c | 2 +- gcc/testsuite/gcc.target/riscv/attribute-18.c | 2 +- gcc/testsuite/gcc.target/riscv/pr110696.c | 2 +- .../gcc.target/riscv/rvv/base/pr114352-1.c | 4 +-- .../gcc.target/riscv/rvv/base/pr114352-3.c | 8 ++--- 11 files changed, 41 insertions(+), 29 deletions(-) diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 88204393fde..78dfd6b1470 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -79,6 +79,9 @@ static const riscv_implied_info_t riscv_implied_info[] = {"f", "zicsr"}, {"d", "zicsr"}, + {"a", "zaamo"}, + {"a", "zalrsc"}, + {"zdinx", "zfinx"}, {"zfinx", "zicsr"}, {"zdinx", "zicsr"}, @@ -255,6 +258,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"za64rs", ISA_SPEC_CLASS_NONE, 1, 0}, {"za128rs", ISA_SPEC_CLASS_NONE, 1, 0}, {"zawrs", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zaamo", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zalrsc", ISA_SPEC_CLASS_NONE, 1, 0}, {"zba", ISA_SPEC_CLASS_NONE, 1, 0}, {"zbb", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1616,9 +1621,11 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI}, {"zicond", &gcc_options::x_riscv_zi_subext, MASK_ZICOND}, - {"za64rs", &gcc_options::x_riscv_za_subext, MASK_ZA64RS}, + {"za64rs", &gcc_options::x_riscv_za_subext, MASK_ZA64RS}, {"za128rs", &gcc_options::x_riscv_za_subext, MASK_ZA128RS}, - {"zawrs", &gcc_options::x_riscv_za_subext, MASK_ZAWRS}, + {"zawrs", &gcc_options::x_riscv_za_subext, MASK_ZAWRS}, + {"zaamo", &gcc_options::x_riscv_za_subext, MASK_ZAAMO}, + {"zalrsc", &gcc_options::x_riscv_za_subext, MASK_ZALRSC}, {"zba", &gcc_options::x_riscv_zb_subext, MASK_ZBA}, {"zbb", &gcc_options::x_riscv_zb_subext, MASK_ZBB}, diff --git a/gcc/config/riscv/arch-canonicalize b/gcc/config/riscv/arch-canonicalize index 8f7d040cdeb..6c10d1aa81b 100755 --- a/gcc/config/riscv/arch-canonicalize +++ b/gcc/config/riscv/arch-canonicalize @@ -40,6 +40,7 @@ LONG_EXT_PREFIXES = ['z', 's', 'h', 'x'] # IMPLIED_EXT = { "d" : ["f", "zicsr"], + "a" : ["zaamo", "zalrsc"], "f" : ["zicsr"], "zdinx" : ["zfinx", "zicsr"], "zfinx" : ["zicsr"], diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 78cb1c37e69..b13e993c47a 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -256,7 +256,11 @@ Mask(ZICCRSE) Var(riscv_zi_subext) TargetVariable int riscv_za_subext -Mask(ZAWRS) Var(riscv_za_subext) +Mask(ZAWRS) Var(riscv_za_subext) + +Mask(ZAAMO) Var(riscv_za_subext) + +Mask(ZALRSC) Var(riscv_za_subext) Mask(ZA64RS) Var(riscv_za_subext) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 6f0b5aae08d..c9544176ead 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -93,7 +93,7 @@ (match_operand:GPR 1 "reg_or_0_operand" "rJ")) (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] - "TARGET_ATOMIC" + "TARGET_ZAAMO" "amo.%A2\tzero,%z1,%0" [(set_attr "type" "atomic") (set (attr "length") (const_int 4))]) @@ -107,7 +107,7 @@ (match_operand:GPR 2 "reg_or_0_operand" "rJ")) (match_operand:SI 3 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] - "TARGET_ATOMIC" + "TARGET_ZAAMO" "amo.%A3\t%0,%z2,%1" [(set_attr "type" "atomic") (set (attr "length") (const_int 4))]) @@ -125,7 +125,7 @@ (match_operand:SI 5 "register_operand" "rI") ;; not_mask (clobber (match_scratch:SI 6 "=&r")) ;; tmp_1 (clobber (match_scratch:SI 7 "=&r"))] ;; tmp_2 - "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" + "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" { return "1:\;" "lr.w%I3\t%0, %1\;" @@ -144,7 +144,7 @@ (not:SHORT (and:SHORT (match_operand:SHORT 1 "memory_operand") ;; mem location (match_operand:SHORT 2 "reg_or_0_operand"))) ;; value for op (match_operand:SI 3 "const_int_operand")] ;; model - "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" + "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" { /* We have no QImode/HImode atomics, so form a mask, then use subword_atomic_fetch_strong_nand to implement a LR/SC version of the @@ -192,7 +192,7 @@ (match_operand:SI 5 "register_operand" "rI") ;; not_mask (clobber (match_scratch:SI 6 "=&r")) ;; tmp_1 (clobber (match_scratch:SI 7 "=&r"))] ;; tmp_2 - "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" + "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" { return "1:\;" "lr.w%I3\t%0, %1\;" @@ -212,7 +212,7 @@ (any_atomic:SHORT (match_operand:SHORT 1 "memory_operand") ;; mem location (match_operand:SHORT 2 "reg_or_0_operand")) ;; value for op (match_operand:SI 3 "const_int_operand")] ;; model - "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" + "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" { /* We have no QImode/HImode atomics, so form a mask, then use subword_atomic_fetch_strong_ to implement a LR/SC version of the @@ -256,7 +256,7 @@ UNSPEC_SYNC_EXCHANGE)) (set (match_dup 1) (match_operand:GPR 2 "register_operand" "0"))] - "TARGET_ATOMIC" + "TARGET_ZAAMO" "amoswap.%A3\t%0,%z2,%1" [(set_attr "type" "atomic") (set (attr "length") (const_int 4))]) @@ -266,7 +266,7 @@ (match_operand:SHORT 1 "memory_operand") ;; mem location (match_operand:SHORT 2 "register_operand") ;; value (match_operand:SI 3 "const_int_operand")] ;; model - "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" + "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" { rtx old = gen_reg_rtx (SImode); rtx mem = operands[1]; @@ -303,7 +303,7 @@ UNSPEC_SYNC_EXCHANGE_SUBWORD)) (match_operand:SI 4 "reg_or_0_operand" "rI") ;; not_mask (clobber (match_scratch:SI 5 "=&r"))] ;; tmp_1 - "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" + "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" { return "1:\;" "lr.w%I3\t%0, %1\;" @@ -325,7 +325,7 @@ (match_operand:SI 5 "const_int_operand")] ;; mod_f UNSPEC_COMPARE_AND_SWAP)) (clobber (match_scratch:GPR 6 "=&r"))] - "TARGET_ATOMIC" + "TARGET_ZALRSC" { enum memmodel model_success = (enum memmodel) INTVAL (operands[4]); enum memmodel model_failure = (enum memmodel) INTVAL (operands[5]); @@ -351,7 +351,7 @@ (match_operand:SI 5 "const_int_operand" "") ;; is_weak (match_operand:SI 6 "const_int_operand" "") ;; mod_s (match_operand:SI 7 "const_int_operand" "")] ;; mod_f - "TARGET_ATOMIC" + "TARGET_ZALRSC" { if (word_mode != mode && operands[3] != const0_rtx) { @@ -394,7 +394,7 @@ (match_operand:SI 5 "const_int_operand") ;; is_weak (match_operand:SI 6 "const_int_operand") ;; mod_s (match_operand:SI 7 "const_int_operand")] ;; mod_f - "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" + "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" { emit_insn (gen_atomic_cas_value_strong (operands[1], operands[2], operands[3], operands[4], @@ -439,7 +439,7 @@ (match_operand:SI 4 "const_int_operand") ;; mod_s (match_operand:SI 5 "const_int_operand") ;; mod_f (match_scratch:SHORT 6)] - "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" + "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" { /* We have no QImode/HImode atomics, so form a mask, then use subword_atomic_cas_strong to implement a LR/SC version of the @@ -497,7 +497,7 @@ (match_operand:SI 5 "register_operand" "rI") ;; mask (match_operand:SI 6 "register_operand" "rI") ;; not_mask (clobber (match_scratch:SI 7 "=&r"))] ;; tmp_1 - "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" + "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" { return "1:\;" "lr.w%I4\t%0, %1\;" @@ -516,7 +516,7 @@ [(match_operand:QI 0 "register_operand" "") ;; bool output (match_operand:QI 1 "memory_operand" "+A") ;; memory (match_operand:SI 2 "const_int_operand" "")] ;; model - "TARGET_ATOMIC" + "TARGET_ZALRSC" { /* We have no QImode atomics, so use the address LSBs to form a mask, then use an aligned SImode atomic. */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-15.c b/gcc/testsuite/gcc.target/riscv/attribute-15.c index 59efeb6ea45..a2e394b6489 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-15.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-15.c @@ -3,4 +3,4 @@ int foo() { } -/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0\"" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-16.c b/gcc/testsuite/gcc.target/riscv/attribute-16.c index 26f961efb48..d2b18160cb5 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-16.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-16.c @@ -3,4 +3,4 @@ int foo() { } -/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p0_f2p2_d2p2_c2p0_zicsr2p0" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p0_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-17.c b/gcc/testsuite/gcc.target/riscv/attribute-17.c index 0abff3705d9..fc2f488a3ac 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-17.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-17.c @@ -3,4 +3,4 @@ int foo() { } -/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-18.c b/gcc/testsuite/gcc.target/riscv/attribute-18.c index fddbf15fc3e..eefd602103d 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-18.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-18.c @@ -1,4 +1,4 @@ /* { dg-do compile } */ /* { dg-options "-mriscv-attribute -march=rv64imafdc -mabi=lp64d -misa-spec=2.2" } */ int foo() {} -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0\"" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr110696.c b/gcc/testsuite/gcc.target/riscv/pr110696.c index a630f04e74f..08682a047e0 100644 --- a/gcc/testsuite/gcc.target/riscv/pr110696.c +++ b/gcc/testsuite/gcc.target/riscv/pr110696.c @@ -4,4 +4,4 @@ int foo() { } -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c index b3f1f20fb79..faeb406498d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c @@ -54,5 +54,5 @@ test_3 (int *a, int *b, int *out, unsigned count) out[i] = a[i] + b[i]; } -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0\"" } } */ -/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */ +/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c index e7af4223d6a..38815ef5bd0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c @@ -107,7 +107,7 @@ test_6 (_Float16 *a, _Float16 *b, _Float16 *out, unsigned count) out[i] = a[i] + b[i]; } -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0\"" } } */ -/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */ -/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zbb1p0" } } */ -/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zfh1p0_zfhmin1p0" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */ +/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */ +/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zbb1p0" } } */ +/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zfh1p0_zfhmin1p0" } } */