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Tue, 04 Jun 2024 01:09:49 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 45419mHh004592 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 4 Jun 2024 01:09:48 GMT Received: from hu-pzheng-lv.qualcomm.com (10.49.16.6) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 3 Jun 2024 18:09:48 -0700 From: Pengxuan Zheng To: CC: Pengxuan Zheng Subject: [PATCH] aarch64: Add fix_truncv4sfv4hi2 pattern [PR113882] Date: Mon, 3 Jun 2024 18:09:24 -0700 Message-ID: <20240604010924.12123-1-quic_pzheng@quicinc.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Wi63zxodmEUfsgRtRFEww6LMUONMjpLv X-Proofpoint-GUID: Wi63zxodmEUfsgRtRFEww6LMUONMjpLv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.12.28.16 definitions=2024-06-03_17,2024-05-30_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 bulkscore=0 spamscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 clxscore=1015 malwarescore=0 phishscore=0 mlxscore=0 lowpriorityscore=0 mlxlogscore=784 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2406040007 X-Spam-Status: No, score=-13.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org This patch adds the fix_truncv4sfv4hi2 (V4SF->V4HI) pattern which is implemented using fix_truncv4sfv4si2 (V4SF->V4SI) and then truncv4siv4hi2 (V4SI->V4HI). PR target/113882 gcc/ChangeLog: * config/aarch64/aarch64-simd.md (fix_truncv4sfv4hi2): New pattern. gcc/testsuite/ChangeLog: * gcc.target/aarch64/fix_trunc2.c: New test. Signed-off-by: Pengxuan Zheng --- gcc/config/aarch64/aarch64-simd.md | 13 +++++++++++++ gcc/testsuite/gcc.target/aarch64/fix_trunc2.c | 14 ++++++++++++++ 2 files changed, 27 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/fix_trunc2.c diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 868f4486218..096f7b56a27 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -3032,6 +3032,19 @@ (define_expand "2" "TARGET_SIMD" {}) + +(define_expand "fix_truncv4sfv4hi2" + [(match_operand:V4HI 0 "register_operand") + (match_operand:V4SF 1 "register_operand")] + "TARGET_SIMD" + { + rtx tmp = gen_reg_rtx (V4SImode); + emit_insn (gen_fix_truncv4sfv4si2 (tmp, operands[1])); + emit_insn (gen_truncv4siv4hi2 (operands[0], tmp)); + DONE; + } +) + (define_expand "ftrunc2" [(set (match_operand:VHSDF 0 "register_operand") (unspec:VHSDF [(match_operand:VHSDF 1 "register_operand")] diff --git a/gcc/testsuite/gcc.target/aarch64/fix_trunc2.c b/gcc/testsuite/gcc.target/aarch64/fix_trunc2.c new file mode 100644 index 00000000000..57cc00913a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fix_trunc2.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +void +f (short *__restrict a, float *__restrict b) +{ + a[0] = b[0]; + a[1] = b[1]; + a[2] = b[2]; + a[3] = b[3]; +} + +/* { dg-final { scan-assembler-times {fcvtzs\tv[0-9]+.4s, v[0-9]+.4s} 1 } } */ +/* { dg-final { scan-assembler-times {xtn\tv[0-9]+.4h, v[0-9]+.4s} 1 } } */