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Thu, 30 May 2024 03:47:46 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 44U3li46004933 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 30 May 2024 03:47:44 GMT Received: from hu-apinski-lv.qualcomm.com (10.49.16.6) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 29 May 2024 20:47:44 -0700 From: Andrew Pinski To: CC: Andrew Pinski Subject: [PATCH] Fix some opindex for some options [PR115022] Date: Wed, 29 May 2024 20:47:30 -0700 Message-ID: <20240530034730.2645990-1-quic_apinski@quicinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ut2amdEcREpMqFm0DB4f1uJIb8aigjLe X-Proofpoint-ORIG-GUID: ut2amdEcREpMqFm0DB4f1uJIb8aigjLe X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.12.28.16 definitions=2024-05-29_16,2024-05-28_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=0 priorityscore=1501 bulkscore=0 phishscore=0 adultscore=0 spamscore=0 mlxlogscore=999 malwarescore=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2405300027 X-Spam-Status: No, score=-13.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org While looking at the index I noticed that some options had `-` in the front for the index which is wrong. And then I noticed there was no index for `mcmodel=` for targets or had used `-mcmodel` incorrectly. This fixes both of those and regnerates the urls files see that `-mcmodel=` option now has an url associated with it. OK? gcc/ChangeLog: PR target/115022 * doc/invoke.texi (fstrub=disable): Fix opindex. (minline-memops-threshold): Fix opindex. (mcmodel=): Add opindex and fix them. * common.opt.urls: Regenerate. * config/aarch64/aarch64.opt.urls: Regenerate. * config/bpf/bpf.opt.urls: Regenerate. * config/i386/i386.opt.urls: Regenerate. * config/loongarch/loongarch.opt.urls: Regenerate. * config/nds32/nds32-elf.opt.urls: Regenerate. * config/nds32/nds32-linux.opt.urls: Regenerate. * config/or1k/or1k.opt.urls: Regenerate. * config/riscv/riscv.opt.urls: Regenerate. * config/rs6000/aix64.opt.urls: Regenerate. * config/rs6000/linux64.opt.urls: Regenerate. * config/sparc/sparc.opt.urls: Regenerate. Signed-off-by: Andrew Pinski --- gcc/common.opt.urls | 3 +++ gcc/config/aarch64/aarch64.opt.urls | 3 ++- gcc/config/bpf/bpf.opt.urls | 3 +++ gcc/config/i386/i386.opt.urls | 3 ++- gcc/config/loongarch/loongarch.opt.urls | 2 +- gcc/config/nds32/nds32-elf.opt.urls | 2 +- gcc/config/nds32/nds32-linux.opt.urls | 2 +- gcc/config/or1k/or1k.opt.urls | 3 ++- gcc/config/riscv/riscv.opt.urls | 3 ++- gcc/config/rs6000/aix64.opt.urls | 3 ++- gcc/config/rs6000/linux64.opt.urls | 3 ++- gcc/config/sparc/sparc.opt.urls | 2 +- gcc/doc/invoke.texi | 17 +++++++++++------ 13 files changed, 33 insertions(+), 16 deletions(-) diff --git a/gcc/common.opt.urls b/gcc/common.opt.urls index 10462e40874..1f2eb67c8e0 100644 --- a/gcc/common.opt.urls +++ b/gcc/common.opt.urls @@ -1339,6 +1339,9 @@ UrlSuffix(gcc/Optimize-Options.html#index-fstrict-aliasing) fstrict-overflow UrlSuffix(gcc/Code-Gen-Options.html#index-fstrict-overflow) +fstrub=disable +UrlSuffix(gcc/Instrumentation-Options.html#index-fstrub_003ddisable) + fstrub=strict UrlSuffix(gcc/Instrumentation-Options.html#index-fstrub_003dstrict) diff --git a/gcc/config/aarch64/aarch64.opt.urls b/gcc/config/aarch64/aarch64.opt.urls index 993634c52f8..4fa90384378 100644 --- a/gcc/config/aarch64/aarch64.opt.urls +++ b/gcc/config/aarch64/aarch64.opt.urls @@ -18,7 +18,8 @@ UrlSuffix(gcc/AArch64-Options.html#index-mfix-cortex-a53-843419) mlittle-endian UrlSuffix(gcc/AArch64-Options.html#index-mlittle-endian) -; skipping UrlSuffix for 'mcmodel=' due to finding no URLs +mcmodel= +UrlSuffix(gcc/AArch64-Options.html#index-mcmodel_003d) mtp= UrlSuffix(gcc/AArch64-Options.html#index-mtp) diff --git a/gcc/config/bpf/bpf.opt.urls b/gcc/config/bpf/bpf.opt.urls index 8c1e5f86d5c..1e8873a899f 100644 --- a/gcc/config/bpf/bpf.opt.urls +++ b/gcc/config/bpf/bpf.opt.urls @@ -33,3 +33,6 @@ UrlSuffix(gcc/eBPF-Options.html#index-msmov) mcpu= UrlSuffix(gcc/eBPF-Options.html#index-mcpu-5) +minline-memops-threshold= +UrlSuffix(gcc/eBPF-Options.html#index-minline-memops-threshold) + diff --git a/gcc/config/i386/i386.opt.urls b/gcc/config/i386/i386.opt.urls index 40e8a844936..9384b0b3187 100644 --- a/gcc/config/i386/i386.opt.urls +++ b/gcc/config/i386/i386.opt.urls @@ -40,7 +40,8 @@ UrlSuffix(gcc/x86-Options.html#index-march-16) mlarge-data-threshold= UrlSuffix(gcc/x86-Options.html#index-mlarge-data-threshold) -; skipping UrlSuffix for 'mcmodel=' due to finding no URLs +mcmodel= +UrlSuffix(gcc/x86-Options.html#index-mcmodel_003d-7) mcpu= UrlSuffix(gcc/x86-Options.html#index-mcpu-14) diff --git a/gcc/config/loongarch/loongarch.opt.urls b/gcc/config/loongarch/loongarch.opt.urls index 9ed5d7b5596..f7545f65103 100644 --- a/gcc/config/loongarch/loongarch.opt.urls +++ b/gcc/config/loongarch/loongarch.opt.urls @@ -58,7 +58,7 @@ mrecip UrlSuffix(gcc/LoongArch-Options.html#index-mrecip) mcmodel= -UrlSuffix(gcc/LoongArch-Options.html#index-mcmodel) +UrlSuffix(gcc/LoongArch-Options.html#index-mcmodel_003d-1) mdirect-extern-access UrlSuffix(gcc/LoongArch-Options.html#index-mdirect-extern-access) diff --git a/gcc/config/nds32/nds32-elf.opt.urls b/gcc/config/nds32/nds32-elf.opt.urls index 3ae1efe7312..e5432b62863 100644 --- a/gcc/config/nds32/nds32-elf.opt.urls +++ b/gcc/config/nds32/nds32-elf.opt.urls @@ -1,5 +1,5 @@ ; Autogenerated by regenerate-opt-urls.py from gcc/config/nds32/nds32-elf.opt and generated HTML mcmodel= -UrlSuffix(gcc/NDS32-Options.html#index-mcmodel-1) +UrlSuffix(gcc/NDS32-Options.html#index-mcmodel_003d-2) diff --git a/gcc/config/nds32/nds32-linux.opt.urls b/gcc/config/nds32/nds32-linux.opt.urls index ac589ccd472..3986cf225ef 100644 --- a/gcc/config/nds32/nds32-linux.opt.urls +++ b/gcc/config/nds32/nds32-linux.opt.urls @@ -1,5 +1,5 @@ ; Autogenerated by regenerate-opt-urls.py from gcc/config/nds32/nds32-linux.opt and generated HTML mcmodel= -UrlSuffix(gcc/NDS32-Options.html#index-mcmodel-1) +UrlSuffix(gcc/NDS32-Options.html#index-mcmodel_003d-2) diff --git a/gcc/config/or1k/or1k.opt.urls b/gcc/config/or1k/or1k.opt.urls index 2016ea622cf..b3ba2df4ab7 100644 --- a/gcc/config/or1k/or1k.opt.urls +++ b/gcc/config/or1k/or1k.opt.urls @@ -24,7 +24,8 @@ UrlSuffix(gcc/OpenRISC-Options.html#index-mdouble-float-3) munordered-float UrlSuffix(gcc/OpenRISC-Options.html#index-munordered-float) -; skipping UrlSuffix for 'mcmodel=' due to finding no URLs +mcmodel= +UrlSuffix(gcc/OpenRISC-Options.html#index-mcmodel_003d-3) mcmov UrlSuffix(gcc/OpenRISC-Options.html#index-mcmov-1) diff --git a/gcc/config/riscv/riscv.opt.urls b/gcc/config/riscv/riscv.opt.urls index e02ef3ee3dd..d87e9d5c9a8 100644 --- a/gcc/config/riscv/riscv.opt.urls +++ b/gcc/config/riscv/riscv.opt.urls @@ -41,7 +41,8 @@ UrlSuffix(gcc/RISC-V-Options.html#index-msave-restore) mshorten-memrefs UrlSuffix(gcc/RISC-V-Options.html#index-mshorten-memrefs) -; skipping UrlSuffix for 'mcmodel=' due to finding no URLs +mcmodel= +UrlSuffix(gcc/RISC-V-Options.html#index-mcmodel_003d-4) mstrict-align UrlSuffix(gcc/RISC-V-Options.html#index-mstrict-align-4) diff --git a/gcc/config/rs6000/aix64.opt.urls b/gcc/config/rs6000/aix64.opt.urls index 89600bb2795..86420ea4a92 100644 --- a/gcc/config/rs6000/aix64.opt.urls +++ b/gcc/config/rs6000/aix64.opt.urls @@ -6,7 +6,8 @@ UrlSuffix(gcc/RS_002f6000-and-PowerPC-Options.html#index-maix64) maix32 UrlSuffix(gcc/RS_002f6000-and-PowerPC-Options.html#index-maix32) -; skipping UrlSuffix for 'mcmodel=' due to finding no URLs +mcmodel= +UrlSuffix(gcc/RS_002f6000-and-PowerPC-Options.html#index-mcmodel_003d-5) mpe UrlSuffix(gcc/RS_002f6000-and-PowerPC-Options.html#index-mpe) diff --git a/gcc/config/rs6000/linux64.opt.urls b/gcc/config/rs6000/linux64.opt.urls index eb81aa17fd2..05b5f3d85f3 100644 --- a/gcc/config/rs6000/linux64.opt.urls +++ b/gcc/config/rs6000/linux64.opt.urls @@ -1,4 +1,5 @@ ; Autogenerated by regenerate-opt-urls.py from gcc/config/rs6000/linux64.opt and generated HTML -; skipping UrlSuffix for 'mcmodel=' due to finding no URLs +mcmodel= +UrlSuffix(gcc/RS_002f6000-and-PowerPC-Options.html#index-mcmodel_003d-5) diff --git a/gcc/config/sparc/sparc.opt.urls b/gcc/config/sparc/sparc.opt.urls index 5a3e9d771b0..24cc22e4cbc 100644 --- a/gcc/config/sparc/sparc.opt.urls +++ b/gcc/config/sparc/sparc.opt.urls @@ -84,7 +84,7 @@ mtune= UrlSuffix(gcc/SPARC-Options.html#index-mtune-15) mcmodel= -UrlSuffix(gcc/SPARC-Options.html#index-mcmodel-2) +UrlSuffix(gcc/SPARC-Options.html#index-mcmodel_003d-6) ; skipping UrlSuffix for 'mdebug=' due to finding no URLs diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 517a782987d..45115b5fbed 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -18248,7 +18248,7 @@ without @option{-fsplit-stack} always has a large stack. Support for this is implemented in the gold linker in GNU binutils release 2.21 and later. -@opindex -fstrub=disable +@opindex fstrub=disable @item -fstrub=disable Disable stack scrubbing entirely, ignoring any @code{strub} attributes. See @xref{Common Type Attributes}. @@ -21185,6 +21185,7 @@ impose any restrictions on the assembler. Generate little-endian code. This is the default when GCC is configured for an @samp{aarch64-*-*} but not an @samp{aarch64_be-*-*} target. +@opindex mcmodel= @opindex mcmodel=tiny @item -mcmodel=tiny Generate code for the tiny code model. The program and its statically defined @@ -25832,7 +25833,7 @@ Outputs pseudo-c assembly dialect. @end table -@opindex -minline-memops-threshold +@opindex minline-memops-threshold @item -minline-memops-threshold=@var{bytes} Specifies a size threshold in bytes at or below which memmove, memcpy and memset shall always be expanded inline. Operations dealing with @@ -27092,7 +27093,7 @@ section (on some targets). The default value is 0. Inline all block moves (such as calls to @code{memcpy} or structure copies) less than or equal to @var{n} bytes. The default value of @var{n} is 1024. -@opindex mcmodel +@opindex mcmodel= @item -mcmodel=@var{code-model} Set the code model to one of: @table @samp @@ -29631,7 +29632,7 @@ which must be a power of 2 between 4 and 512. @item -march=@var{arch} Specify the name of the target architecture. -@opindex mcmodel +@opindex mcmodel= @item -mcmodel=@var{code-model} Set the code model to one of @table @asis @@ -30232,6 +30233,7 @@ Enable generation of shift with immediate (@code{l.srai}, @code{l.srli}, @code{l.slli}) instructions. By default extra instructions will be generated to store the immediate to a register first. +@opindex mcmodel= @opindex mcmodel=small @item -mcmodel=small Generate OpenRISC code for the small model: The GOT is limited to 64k. This is @@ -31102,6 +31104,7 @@ Do not or do generate unaligned memory accesses. The default is set depending on whether the processor we are optimizing for supports fast unaligned access or not. +@opindex mcmodel= @opindex mcmodel=medlow @item -mcmodel=medlow Generate code for the medium-low code model. The program and its statically @@ -31119,7 +31122,7 @@ The code generated by the medium-any code model is position-independent, but is not guaranteed to function correctly when linked into position-independent executables or libraries. -@opindex -mcmodel=large +@opindex mcmodel=large @item -mcmodel=large Generate code for a large code model, which has no restrictions on size or placement of symbols. @@ -31450,6 +31453,7 @@ values for @var{cpu_type} are used for @option{-mtune} as for architecture and registers set by @option{-mcpu}, but the scheduling parameters set by @option{-mtune}. +@opindex mcmodel= @opindex mcmodel=small @item -mcmodel=small Generate PowerPC64 code for the small model: The TOC is limited to @@ -33782,7 +33786,7 @@ The 32-bit environment sets int, long and pointer to 32 bits. The 64-bit environment sets int to 32 bits and long and pointer to 64 bits. -@opindex mcmodel +@opindex mcmodel= @item -mcmodel=@var{which} Set the code model to one of @@ -36286,6 +36290,7 @@ stack pointer that is not modified by signal or interrupt handlers and therefore can be used for temporary data without adjusting the stack pointer. The flag @option{-mno-red-zone} disables this red zone. +@opindex mcmodel= @opindex mcmodel=small @item -mcmodel=small Generate code for the small code model: the program and its symbols must