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X-CSE-ConnectionGUID: qP2i/sCHSzW0C3fmYR2e4w== X-CSE-MsgGUID: XnaPHDs5QtejDzKQJ8+Iuw== X-IronPort-AV: E=McAfee;i="6600,9927,11085"; a="38717181" X-IronPort-AV: E=Sophos;i="6.08,197,1712646000"; d="scan'208";a="38717181" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 May 2024 20:05:02 -0700 X-CSE-ConnectionGUID: hiuOVt4yTi6U7yuQPVmDbQ== X-CSE-MsgGUID: 1URwy6kYRDmvKxvVcEP/hQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,197,1712646000"; d="scan'208";a="35885797" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orviesa007.jf.intel.com with ESMTP; 28 May 2024 20:05:01 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id DA28F1006FE2; Wed, 29 May 2024 11:04:59 +0800 (CST) From: Haochen Jiang To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com, ubizjak@gmail.com Subject: [PATCH] Add AVX10.1 target_clones support Date: Wed, 29 May 2024 11:04:59 +0800 Message-Id: <20240529030459.4015833-1-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Hi all, Since AVX10 is the first major ISA introduced after AVX-512, we propose to add target_clones support for it. Although AVX10.1-256 won't cover 512-bit part of AVX512F, but since it is only for priority but not for implication, it won't be an issue. Bootstrapped and regtested on x86_64-pc-linux-gnu. Ok for trunk and backport to GCC14? Thx, hAOCHEN gcc/ChangeLog: * common/config/i386/i386-common.cc: Change Granite Rapids series CPU type to P_PROC_AVX10_1_512. * common/config/i386/i386-cpuinfo.h (enum feature_priority): Revise comment part. Add P_AVX10_1_256, P_AVX10_1_512, P_PROC_AVX10_1_512. * common/config/i386/i386-isas.h: Link to avx10.1-256, avx10.1-512. gcc/testsuite/ChangeLog: * gcc.target/i386/avx10_1-25.c: New test. * gcc.target/i386/avx10_1-26.c: Ditto. --- gcc/common/config/i386/i386-common.cc | 4 ++-- gcc/common/config/i386/i386-cpuinfo.h | 5 ++++- gcc/common/config/i386/i386-isas.h | 4 ++-- gcc/testsuite/gcc.target/i386/avx10_1-25.c | 9 +++++++++ gcc/testsuite/gcc.target/i386/avx10_1-26.c | 9 +++++++++ 5 files changed, 26 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-25.c create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-26.c diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc index 77b154663bc..d578918dfb7 100644 --- a/gcc/common/config/i386/i386-common.cc +++ b/gcc/common/config/i386/i386-common.cc @@ -2273,10 +2273,10 @@ const pta processor_alias_table[] = {"meteorlake", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE, M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2}, {"graniterapids", PROCESSOR_GRANITERAPIDS, CPU_HASWELL, PTA_GRANITERAPIDS, - M_CPU_SUBTYPE (INTEL_COREI7_GRANITERAPIDS), P_PROC_AVX512F}, + M_CPU_SUBTYPE (INTEL_COREI7_GRANITERAPIDS), P_PROC_AVX10_1_512}, {"graniterapids-d", PROCESSOR_GRANITERAPIDS_D, CPU_HASWELL, PTA_GRANITERAPIDS_D, M_CPU_SUBTYPE (INTEL_COREI7_GRANITERAPIDS_D), - P_PROC_AVX512F}, + P_PROC_AVX10_1_512}, {"arrowlake", PROCESSOR_ARROWLAKE, CPU_HASWELL, PTA_ARROWLAKE, M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE), P_PROC_AVX2}, {"arrowlake-s", PROCESSOR_ARROWLAKE_S, CPU_HASWELL, PTA_ARROWLAKE_S, diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h index 73131657eab..be52ad2c60d 100644 --- a/gcc/common/config/i386/i386-cpuinfo.h +++ b/gcc/common/config/i386/i386-cpuinfo.h @@ -112,7 +112,7 @@ enum processor_subtypes /* Priority of i386 features, greater value is higher priority. This is used to decide the order in which function dispatch must happen. For instance, a version specialized for SSE4.2 should be checked for dispatch - before a version for SSE3, as SSE4.2 implies SSE3. */ + before a version for SSE3. */ enum feature_priority { P_NONE = 0, @@ -148,6 +148,9 @@ enum feature_priority P_AVX512F, P_PROC_AVX512F, P_X86_64_V4, + P_AVX10_1_256, + P_AVX10_1_512, + P_PROC_AVX10_1_512, P_PROC_DYNAMIC }; diff --git a/gcc/common/config/i386/i386-isas.h b/gcc/common/config/i386/i386-isas.h index d6deb9a1522..9c2179a3dd8 100644 --- a/gcc/common/config/i386/i386-isas.h +++ b/gcc/common/config/i386/i386-isas.h @@ -194,6 +194,6 @@ ISA_NAMES_TABLE_START ISA_NAMES_TABLE_ENTRY("apxf", FEATURE_APX_F, P_NONE, "-mapxf") ISA_NAMES_TABLE_ENTRY("usermsr", FEATURE_USER_MSR, P_NONE, "-musermsr") ISA_NAMES_TABLE_ENTRY("avx10.1", FEATURE_AVX10_1_256, P_NONE, "-mavx10.1") - ISA_NAMES_TABLE_ENTRY("avx10.1-256", FEATURE_AVX10_1_256, P_NONE, "-mavx10.1-256") - ISA_NAMES_TABLE_ENTRY("avx10.1-512", FEATURE_AVX10_1_512, P_NONE, "-mavx10.1-512") + ISA_NAMES_TABLE_ENTRY("avx10.1-256", FEATURE_AVX10_1_256, P_AVX10_1_256, "-mavx10.1-256") + ISA_NAMES_TABLE_ENTRY("avx10.1-512", FEATURE_AVX10_1_512, P_AVX10_1_512, "-mavx10.1-512") ISA_NAMES_TABLE_END diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-25.c b/gcc/testsuite/gcc.target/i386/avx10_1-25.c new file mode 100644 index 00000000000..73f1b724560 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-25.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx" } */ + +#include +__attribute__((target_clones ("default","avx10.1-256"))) +__m256d foo(__m256d a, __m256d b) +{ + return a + b; +} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-26.c b/gcc/testsuite/gcc.target/i386/avx10_1-26.c new file mode 100644 index 00000000000..514ab57a406 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-26.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512f" } */ + +#include +__attribute__((target_clones ("default","avx10.1-512"))) +__m512d foo(__m512d a, __m512d b) +{ + return a + b; +}