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X-CSE-ConnectionGUID: p1Sjn0STSb2qvilkdDSNNQ== X-CSE-MsgGUID: ue/4BLJ8SXqa1hI/aa5zag== X-IronPort-AV: E=McAfee;i="6600,9927,11073"; a="29302479" X-IronPort-AV: E=Sophos;i="6.08,161,1712646000"; d="scan'208";a="29302479" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 23:24:17 -0700 X-CSE-ConnectionGUID: CA4D8Tl6SnyviR8t7s5F1Q== X-CSE-MsgGUID: UlzgCaQKTcmLBh9yzwS2tg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,161,1712646000"; d="scan'208";a="62117538" Received: from scymds04.sc.intel.com ([10.82.73.238]) by fmviesa001.fm.intel.com with ESMTP; 14 May 2024 23:24:17 -0700 Received: from shgcc10.sh.intel.com (unknown [10.239.85.189]) by scymds04.sc.intel.com (Postfix) with ESMTP id 52A622003A88; Tue, 14 May 2024 23:24:16 -0700 (PDT) From: "Cui, Lili" To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com, ubizjak@gmail.com Subject: [PATCH 1/2] Add check for 8-bit old registers in EVEX format Date: Wed, 15 May 2024 14:24:13 +0800 Message-Id: <20240515062414.3960582-2-lili.cui@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515062414.3960582-1-lili.cui@intel.com> References: <20240515062414.3960582-1-lili.cui@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org gas/ChangeLog: * config/tc-i386.c (md_assemble): Add invalid check for old byte registers in EVEX/VEX format. * testsuite/gas/i386/x86-64-apx-inval.l: Add new test. * testsuite/gas/i386/x86-64-apx-inval.s: Ditto. --- gas/config/tc-i386.c | 12 ++++++++++++ gas/testsuite/gas/i386/x86-64-apx-inval.l | 3 +++ gas/testsuite/gas/i386/x86-64-apx-inval.s | 2 ++ 3 files changed, 17 insertions(+) diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 339e849a971..18d06371321 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -7029,6 +7029,18 @@ md_assemble (char *line) as_bad (_("{rex2} prefix invalid with `%s'"), insn_name (&i.tm)); return; } + /* Check for 8 bit operand that uses old registers. */ + for (unsigned int op = 0; op < i.operands; op++) + { + if (i.types[op].bitfield.class == Reg + && i.types[op].bitfield.byte + && !(i.op[op].regs->reg_flags & RegRex64) + && i.op[op].regs->reg_num > 3) + + as_bad (_("can't encode register '%s' in an " + " EVEX/VEX prefix instruction"), + i.op[op].regs->reg_name); + } if (is_apx_evex_encoding ()) build_apx_evex_prefix (); diff --git a/gas/testsuite/gas/i386/x86-64-apx-inval.l b/gas/testsuite/gas/i386/x86-64-apx-inval.l index 7a870b27b72..3595213b179 100644 --- a/gas/testsuite/gas/i386/x86-64-apx-inval.l +++ b/gas/testsuite/gas/i386/x86-64-apx-inval.l @@ -12,3 +12,6 @@ .*:13: Error: \{nf\} unsupported for `mulx' .*:14: Error: \{nf\} cannot be combined with \{vex\}/\{vex3\} .*:15: Error: \{nf\} cannot be combined with \{vex\}/\{vex3\} +.*:16: Error: can't encode register 'ah' in an EVEX/VEX prefix instruction +.*:17: Error: can't encode register 'ah' in an EVEX/VEX prefix instruction +#pass diff --git a/gas/testsuite/gas/i386/x86-64-apx-inval.s b/gas/testsuite/gas/i386/x86-64-apx-inval.s index 0487b885ec8..3a8402429ed 100644 --- a/gas/testsuite/gas/i386/x86-64-apx-inval.s +++ b/gas/testsuite/gas/i386/x86-64-apx-inval.s @@ -13,3 +13,5 @@ {nf} mulx %r15,%r15,%r11 {nf} {vex} bextr %ecx, %edx, %r10d {vex} {nf} bextr %ecx, %edx, %r10d + {nf} add %dl,%ah + {evex} adc %dl,%ah