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X-CSE-ConnectionGUID: PJq38pwdRCOZmPb4+G1D2A== X-CSE-MsgGUID: 370ZqLBJQzOJnZv96PGCQQ== X-IronPort-AV: E=McAfee;i="6600,9927,11073"; a="22369362" X-IronPort-AV: E=Sophos;i="6.08,160,1712646000"; d="scan'208";a="22369362" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 20:04:32 -0700 X-CSE-ConnectionGUID: 50yBtQ3uS2aYZbNz/D0zig== X-CSE-MsgGUID: X/W4IogARjW9HUZKVF1QjA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,160,1712646000"; d="scan'208";a="31320617" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orviesa006.jf.intel.com with ESMTP; 14 May 2024 20:04:30 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 3A7CB10077F0; Wed, 15 May 2024 11:04:29 +0800 (CST) From: Haochen Jiang To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com, ubizjak@gmail.com Subject: [PATCH 1/2] Adjust generic loop alignment from 16:11:8 to 16 for Intel processors Date: Wed, 15 May 2024 11:04:28 +0800 Message-Id: <20240515030429.2575440-2-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20240515030429.2575440-1-haochen.jiang@intel.com> References: <20240515030429.2575440-1-haochen.jiang@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Previously, we use 16:11:8 in generic tune for Intel processors, which lead to cross cache line issue and result in some random performance penalty in benchmarks with small loops commit to commit. After changing to always aligning to 16 bytes, it will somehow solve the issue. gcc/ChangeLog: * config/i386/x86-tune-costs.h (generic_cost): Change from 16:11:8 to 16. --- gcc/config/i386/x86-tune-costs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/i386/x86-tune-costs.h b/gcc/config/i386/x86-tune-costs.h index 65d7d1f7e42..d3aaaa4b5cc 100644 --- a/gcc/config/i386/x86-tune-costs.h +++ b/gcc/config/i386/x86-tune-costs.h @@ -3758,7 +3758,7 @@ struct processor_costs generic_cost = { generic_memset, COSTS_N_INSNS (4), /* cond_taken_branch_cost. */ COSTS_N_INSNS (2), /* cond_not_taken_branch_cost. */ - "16:11:8", /* Loop alignment. */ + "16", /* Loop alignment. */ "16:11:8", /* Jump alignment. */ "0:0:8", /* Label alignment. */ "16", /* Func alignment. */