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Wed, 08 May 2024 04:04:39 -0700 (PDT) Received: from localhost.localdomain ([2409:8700:2482:720:5054:ff:fe12:3456]) by smtp.gmail.com with ESMTPSA id m20-20020a170902f21400b001ddc83fda95sm11600777plc.186.2024.05.08.04.04.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 May 2024 04:04:38 -0700 (PDT) From: YunQiang Su To: gcc-patches@gcc.gnu.org Subject: [PATCH] MIPS: Support constraint 'w' for MSA instruction Date: Wed, 8 May 2024 19:04:33 +0800 Message-Id: <20240508110433.1285285-1-syq@gcc.gnu.org> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Support syntax like: asm volatile ("fmadd.d %w0, %w1, %w2" : "+w"(a): "w"(b), "w"(c)); gcc * config/mips/constraints.md: Add new constraint 'w'. gcc/testsuite * gcc.target/mips/msa-inline-asm.c: New test. --- gcc/config/mips/constraints.md | 3 +++ gcc/testsuite/gcc.target/mips/msa-inline-asm.c | 9 +++++++++ 2 files changed, 12 insertions(+) create mode 100644 gcc/testsuite/gcc.target/mips/msa-inline-asm.c diff --git a/gcc/config/mips/constraints.md b/gcc/config/mips/constraints.md index a96028dd746..f5c88179038 100644 --- a/gcc/config/mips/constraints.md +++ b/gcc/config/mips/constraints.md @@ -29,6 +29,9 @@ (define_register_constraint "t" "T_REG" (define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS" "A floating-point register (if available).") +(define_register_constraint "w" "ISA_HAS_MSA ? FP_REGS : NO_REGS" + "A MIPS SIMD register (if available).") + (define_register_constraint "h" "NO_REGS" "Formerly the @code{hi} register. This constraint is no longer supported.") diff --git a/gcc/testsuite/gcc.target/mips/msa-inline-asm.c b/gcc/testsuite/gcc.target/mips/msa-inline-asm.c new file mode 100644 index 00000000000..bdf6816ab3b --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/msa-inline-asm.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-mips16 -mfp64 -mhard-float -mmsa" } */ + +double +f(double a, double b, double c) { + asm volatile ("fmadd.d %w0, %w1, %w2" : "+w"(a): "w"(b), "w"(c)); + return a; +} +/* { dg-final { scan-assembler "fmadd.d \\\$w0, \\\$w\[0-9\]*, \\\$w\[0-9\]*" } } */