From patchwork Sun Apr 28 08:57:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Mei X-Patchwork-Id: 1928613 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=oss.cipunited.com header.i=@oss.cipunited.com header.a=rsa-sha256 header.s=feishu2303200042 header.b=oLwaXu/1; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4VS0ln4lZWz23jG for ; Sun, 28 Apr 2024 19:00:03 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 572793858CD1 for ; Sun, 28 Apr 2024 09:00:01 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from va-2-31.ptr.blmpb.com (va-2-31.ptr.blmpb.com [209.127.231.31]) by sourceware.org (Postfix) with ESMTPS id 0749F3858D20 for ; Sun, 28 Apr 2024 08:59:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0749F3858D20 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=oss.cipunited.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=oss.cipunited.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 0749F3858D20 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=209.127.231.31 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1714294782; cv=none; b=c+rHeJAh7hrAxoCV2LWeGVksYJQL2C8V34lCp65V+Q2dVFnxz0R+LoHDXxRAbBM2MuZa4BVvgXUf5r7Bau8rDazTZ+7+eu8lKnkJex0t7udImypbCefRRzstgwcF9u8rDUuav+lfqJIJObNmEacnHkUuS2AEviynXiUjc47Pmxs= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1714294782; c=relaxed/simple; bh=fSO7CJIZQUTlh7zzJsUEaMhin+wQm0KNBMiy8zqTk2c=; h=DKIM-Signature:From:Date:Message-Id:To:Mime-Version:Subject; b=DXUZ/4D46VOaX97zxANisxtPaWKTisIVeeSVLv73ZZtfMJGMjc3RROh8Nq+mz406KB0KZsMRwi8JAt1mOi7T7Hjb1aAkj6g5MOiY2uxSU1+YjgF8BkKQL8FHq9ONksk1jY0jDrcFtPB8nRoMyLIT/XHT8IyfDR8jDHeXJ0wQZHQ= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=feishu2303200042; d=oss.cipunited.com; t=1714294773; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=IS0ci3eUiK7xR6e1FKi+ozNWlWKxGXBXSwqtlVTJyP8=; b=oLwaXu/1qeea9+kG89KTEktF8ZcP2YQx8kgCdZQ09gCeinejWhZqs+zI+0CmJ28UzfErS/ Z0vttNpzDTx++MdyPf6JnPH3TpwEGkSRBlLD6lsqMczgZPjhY7EESKJo3cGVxpnegwn2/w Cd/NJSFj+vfcduFBinQvCd2yWCFpJiyj2f1pRm6xcNtNn7ajRGIBXnkz2jvGcy72YeSa2m dNOhUK0n1ioi9sP+ZfJ2d1KE90juciL3ePOQ+20Da444H1+njH+iUwZwWEx6nDY+jB3LK3 NZ9rVjB1ynv5WtnEfArv0ipSbdouWFvcU29S5VZI8MANZP9F4R6yA0Db0CUQdw== From: "Jie Mei" Date: Sun, 28 Apr 2024 16:57:31 +0800 Message-Id: <20240428085731.1980105-1-jie.mei@oss.cipunited.com> X-Mailer: git-send-email 2.41.0 To: Received: from fedora.wok.cipunited.com ([123.52.16.97]) by smtp.feishu.cn with ESMTPS; Sun, 28 Apr 2024 16:59:31 +0800 Mime-Version: 1.0 X-Lms-Return-Path: X-Original-From: Jie Mei Cc: "YunQiang Su" , "Xi Ruoyao" Subject: [PATCH v3] MIPS: Add MIN/MAX.fmt instructions support for MIPS R6 X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, DKIM_INVALID, DKIM_SIGNED, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_NUMSUBJECT, KAM_SHORT, MSGID_FROM_MTA_HEADER, RCVD_IN_BARRACUDACENTRAL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org This patch adds the smin/smax RTL mode for the min/max.fmt instructions. Also, since the min/max.fmt instrucions applies to the IEEE 754-2008 "minNum" and "maxNum" operations, this patch also provides the new "fmin3" and "fmax3" modes. gcc/ChangeLog: * config/mips/i6400.md (i6400_fpu_minmax): New define_insn_reservation. * config/mips/mips.h (ISA_HAS_FMIN_FMAX): Define new macro. * config/mips/mips.md (UNSPEC_FMIN): New unspec. (UNSPEC_FMAX): Same as above. (type): Add fminmax. (smin3): Generates MIN.fmt instructions. (smax3): Generates MAX.fmt instructions. (fmin3): Generates MIN.fmt instructions. (fmax3): Generates MAX.fmt instructions. * config/mips/p6600.md (p6600_fpu_fabs): Include fminmax type. gcc/testsuite/ChangeLog: * gcc.target/mips/mips-minmax1.c: New test for MIPS R6. * gcc.target/mips/mips-minmax2.c: Same as above. --- gcc/config/mips/i6400.md | 6 +++ gcc/config/mips/mips.h | 2 + gcc/config/mips/mips.md | 50 +++++++++++++++++++- gcc/config/mips/p6600.md | 4 +- gcc/testsuite/gcc.target/mips/mips-minmax1.c | 40 ++++++++++++++++ gcc/testsuite/gcc.target/mips/mips-minmax2.c | 36 ++++++++++++++ 6 files changed, 134 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/mips/mips-minmax1.c create mode 100644 gcc/testsuite/gcc.target/mips/mips-minmax2.c diff --git a/gcc/config/mips/i6400.md b/gcc/config/mips/i6400.md index 9f216fe0210..d6f691ee217 100644 --- a/gcc/config/mips/i6400.md +++ b/gcc/config/mips/i6400.md @@ -219,6 +219,12 @@ (eq_attr "type" "fabs,fneg,fmove")) "i6400_fpu_short, i6400_fpu_apu") +;; min, max +(define_insn_reservation "i6400_fpu_minmax" 2 + (and (eq_attr "cpu" "i6400") + (eq_attr "type" "fminmax")) + "i6400_fpu_short+i6400_fpu_logic") + ;; fadd, fsub, fcvt (define_insn_reservation "i6400_fpu_fadd" 4 (and (eq_attr "cpu" "i6400") diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 7145d23c650..5ce984ac99b 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -1259,6 +1259,8 @@ struct mips_cpu_info { #define ISA_HAS_9BIT_DISPLACEMENT (mips_isa_rev >= 6 \ || ISA_HAS_MIPS16E2) +#define ISA_HAS_FMIN_FMAX (mips_isa_rev >= 6) + /* ISA has data indexed prefetch instructions. This controls use of 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT. (prefx is a cop1x instruction, so can only be used if FP is diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index b0fb5850a9e..26f758c90dd 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -97,6 +97,10 @@ UNSPEC_GET_FCSR UNSPEC_SET_FCSR + ;; Floating-point unspecs. + UNSPEC_FMIN + UNSPEC_FMAX + ;; HI/LO moves. UNSPEC_MFHI UNSPEC_MTHI @@ -370,6 +374,7 @@ ;; frsqrt floating point reciprocal square root ;; frsqrt1 floating point reciprocal square root step1 ;; frsqrt2 floating point reciprocal square root step2 +;; fminmax floating point min/max ;; dspmac DSP MAC instructions not saturating the accumulator ;; dspmacsat DSP MAC instructions that saturate the accumulator ;; accext DSP accumulator extract instructions @@ -387,8 +392,8 @@ prefetch,prefetchx,condmove,mtc,mfc,mthi,mtlo,mfhi,mflo,const,arith,logical, shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move, fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt, - frsqrt,frsqrt1,frsqrt2,dspmac,dspmacsat,accext,accmod,dspalu,dspalusat, - multi,atomic,syncloop,nop,ghost,multimem, + frsqrt,frsqrt1,frsqrt2,fminmax,dspmac,dspmacsat,accext,accmod,dspalu, + dspalusat,multi,atomic,syncloop,nop,ghost,multimem, simd_div,simd_fclass,simd_flog2,simd_fadd,simd_fcvt,simd_fmul,simd_fmadd, simd_fdiv,simd_bitins,simd_bitmov,simd_insert,simd_sld,simd_mul,simd_fcmp, simd_fexp2,simd_int_arith,simd_bit,simd_shift,simd_splat,simd_fill, @@ -7971,6 +7976,47 @@ [(set_attr "move_type" "load") (set_attr "insn_count" "2")]) +;; +;; Float point MIN/MAX +;; + +(define_insn "smin3" + [(set (match_operand:SCALARF 0 "register_operand" "=f") + (smin:SCALARF (match_operand:SCALARF 1 "register_operand" "f") + (match_operand:SCALARF 2 "register_operand" "f")))] + "ISA_HAS_FMIN_FMAX" + "min.\t%0,%1,%2" + [(set_attr "type" "fminmax") + (set_attr "mode" "")]) + +(define_insn "smax3" + [(set (match_operand:SCALARF 0 "register_operand" "=f") + (smax:SCALARF (match_operand:SCALARF 1 "register_operand" "f") + (match_operand:SCALARF 2 "register_operand" "f")))] + "ISA_HAS_FMIN_FMAX" + "max.\t%0,%1,%2" + [(set_attr "type" "fminmax") + (set_attr "mode" "")]) + +(define_insn "fmin3" + [(set (match_operand:SCALARF 0 "register_operand" "=f") + (unspec:SCALARF [(use (match_operand:SCALARF 1 "register_operand" "f")) + (use (match_operand:SCALARF 2 "register_operand" "f"))] + UNSPEC_FMIN))] + "ISA_HAS_FMIN_FMAX" + "min.\t%0,%1,%2" + [(set_attr "type" "fminmax") + (set_attr "mode" "")]) + +(define_insn "fmax3" + [(set (match_operand:SCALARF 0 "register_operand" "=f") + (unspec:SCALARF [(use (match_operand:SCALARF 1 "register_operand" "f")) + (use (match_operand:SCALARF 2 "register_operand" "f"))] + UNSPEC_FMAX))] + "ISA_HAS_FMIN_FMAX" + "max.\t%0,%1,%2" + [(set_attr "type" "fminmax") + (set_attr "mode" "")]) ;; 2 HI loads are joined. (define_peephole2 diff --git a/gcc/config/mips/p6600.md b/gcc/config/mips/p6600.md index a9e3262cc18..b6cb554939a 100644 --- a/gcc/config/mips/p6600.md +++ b/gcc/config/mips/p6600.md @@ -167,10 +167,10 @@ (eq_attr "type" "fadd")) "p6600_fpu_long, p6600_fpu_apu") -;; fabs, fneg, fcmp +;; fabs, fneg, fcmp, fminmax (define_insn_reservation "p6600_fpu_fabs" 2 (and (eq_attr "cpu" "p6600") - (ior (eq_attr "type" "fabs,fneg,fcmp,fmove") + (ior (eq_attr "type" "fabs,fneg,fcmp,fmove,fminmax") (and (eq_attr "type" "condmove") (eq_attr "mode" "SF,DF")))) "p6600_fpu_short, p6600_fpu_apu") diff --git a/gcc/testsuite/gcc.target/mips/mips-minmax1.c b/gcc/testsuite/gcc.target/mips/mips-minmax1.c new file mode 100644 index 00000000000..087ed299d8f --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/mips-minmax1.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-options "-mhard-float -fno-finite-math-only -march=mips32r6" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +/* Test MIN.D. */ + +/* { dg-final { scan-assembler "\tmin\\.d\t" } } */ +double +test01 (double x, double y) +{ + return __builtin_fmin (x, y); +} + +/* Test MIN.S. */ + +/* { dg-final { scan-assembler "\tmin\\.s\t" } } */ +float +test02 (float x, float y) +{ + return __builtin_fminf (x, y); +} + +/* Test MAX.D. */ + +/* { dg-final { scan-assembler "\tmax\\.d\t" } } */ +double +test03 (double x, double y) +{ + return __builtin_fmax (x, y); +} + +/* Test MAX.S. */ + +/* { dg-final { scan-assembler "\tmax\\.s\t" } } */ +float +test04 (float x, float y) +{ + return __builtin_fmaxf (x, y); +} + diff --git a/gcc/testsuite/gcc.target/mips/mips-minmax2.c b/gcc/testsuite/gcc.target/mips/mips-minmax2.c new file mode 100644 index 00000000000..5359043f06f --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/mips-minmax2.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-options "-mhard-float -march=mips32r6" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +extern double fmin (double, double); +extern double fmax (double, double); +extern float fminf (float, float); +extern float fmaxf (float, float); + +/* Test MIN.D. */ + +/* { dg-final { scan-assembler "\tmin\\.d\t" } } */ +double test01 (double x, double y) { + return fmin (x, y); +} + +/* Test MIN.S. */ + +/* { dg-final { scan-assembler "\tmin\\.s\t" } } */ +float test02 (float x, float y) { + return fminf (x, y); +} + +/* Test MAX.D. */ + +/* { dg-final { scan-assembler "\tmax\\.d\t" } } */ +double test03 (double x, double y) { + return fmax (x, y); +} + +/* Test MAX.S. */ + +/* { dg-final { scan-assembler "\tmax\\.s\t" } } */ +float test04 (float x, float y) { + return fmaxf (x, y); +}