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Fri, 26 Apr 2024 16:10:15 -0700 (PDT) Received: from localhost.localdomain ([139.178.84.207]) by smtp.gmail.com with ESMTPSA id hz12-20020a05687153cc00b0023be82cde3fsm230401oac.20.2024.04.26.16.10.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Apr 2024 16:10:15 -0700 (PDT) From: Christophe Lyon To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com, richard.earnshaw@arm.com, jakub@redhat.com Cc: Christophe Lyon Subject: [PATCH] arm: [MVE intrinsics] Fix support for predicate constants [PR target/114801] Date: Fri, 26 Apr 2024 23:10:12 +0000 Message-Id: <20240426231012.2588918-1-christophe.lyon@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org In this PR, we have to handle a case where MVE predicates are supplied as a const_int, where individual predicates have illegal boolean values (such as 0xc for a 4-bit boolean predicate). To avoid the ICE, we canonicalize them, replacing a non-null value with -1. 2024-04-26 Christophe Lyon Jakub Jelinek PR target/114801 gcc/ * config/arm/arm-mve-builtins.cc (function_expander::add_input_operand): Handle CONST_INT predicates. gcc/testsuite/ * gcc.target/arm/mve/pr114801.c: New test. --- gcc/config/arm/arm-mve-builtins.cc | 21 +++++++++++- gcc/testsuite/gcc.target/arm/mve/pr114801.c | 36 +++++++++++++++++++++ 2 files changed, 56 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/pr114801.c diff --git a/gcc/config/arm/arm-mve-builtins.cc b/gcc/config/arm/arm-mve-builtins.cc index 6a5775c67e5..f338ab36434 100644 --- a/gcc/config/arm/arm-mve-builtins.cc +++ b/gcc/config/arm/arm-mve-builtins.cc @@ -43,6 +43,7 @@ #include "stringpool.h" #include "attribs.h" #include "diagnostic.h" +#include "rtx-vector-builder.h" #include "arm-protos.h" #include "arm-builtins.h" #include "arm-mve-builtins.h" @@ -2205,7 +2206,25 @@ function_expander::add_input_operand (insn_code icode, rtx x) mode = GET_MODE (x); } else if (VALID_MVE_PRED_MODE (mode)) - x = gen_lowpart (mode, x); + { + if (CONST_INT_P (x) && (mode == V8BImode || mode == V4BImode)) + { + /* In V8BI or V4BI each element has 2 or 4 bits, if those + bits aren't all the same, it is UB and gen_lowpart might + ICE. Canonicalize all the 2 or 4 bits to all ones if any + of them is non-zero. */ + unsigned HOST_WIDE_INT xi = UINTVAL (x); + xi |= ((xi & 0x5555) << 1) | ((xi & 0xaaaa) >> 1); + if (mode == V4BImode) + xi |= ((xi & 0x3333) << 2) | ((xi & 0xcccc) >> 2); + x = gen_int_mode (xi, HImode); + } + else if (SUBREG_P (x)) + /* gen_lowpart on a SUBREG can ICE. */ + x = force_reg (GET_MODE (x), x); + + x = gen_lowpart (mode, x); + } m_ops.safe_grow (m_ops.length () + 1, true); create_input_operand (&m_ops.last (), x, mode); diff --git a/gcc/testsuite/gcc.target/arm/mve/pr114801.c b/gcc/testsuite/gcc.target/arm/mve/pr114801.c new file mode 100644 index 00000000000..676b109f9b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/pr114801.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#include + +/* +** test_32: +**... +** mov r[0-9]+, #65535 @ movhi +**... +*/ +uint32x4_t test_32() { + return vdupq_m_n_u32(vdupq_n_u32(0), 0, 0xcccc); +} + +/* +** test_16: +**... +** mov r[0-9]+, #52428 @ movhi +**... +*/ +uint16x8_t test_16() { + return vdupq_m_n_u16(vdupq_n_u16(0), 0, 0xcccc); +} + +/* +** test_8: +**... +** mov r[0-9]+, #52428 @ movhi +**... +*/ +uint8x16_t test_8() { + return vdupq_m_n_u8(vdupq_n_u8(0), 0, 0xcccc); +}