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X-CSE-ConnectionGUID: TQcseYI7Qsut7ztPkd8DbA== X-CSE-MsgGUID: D8ppk5mPTIC98RsU7AoNfg== X-IronPort-AV: E=McAfee;i="6600,9927,11049"; a="9058851" X-IronPort-AV: E=Sophos;i="6.07,215,1708416000"; d="scan'208";a="9058851" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Apr 2024 18:12:07 -0700 X-CSE-ConnectionGUID: B2JEK+SiSyyTovExU3w97A== X-CSE-MsgGUID: FQnuCksxQx+dLzK7T90PPQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,215,1708416000"; d="scan'208";a="28153307" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by fmviesa004.fm.intel.com with ESMTP; 19 Apr 2024 18:12:07 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 2EDAD100567A; Sat, 20 Apr 2024 09:12:06 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v2] RISC-V: Add xfail test case for wv insn register overlap Date: Sat, 20 Apr 2024 09:12:05 +0800 Message-Id: <20240420011205.2025920-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240420010454.2019265-1-pan2.li@intel.com> References: <20240420010454.2019265-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li We reverted below patch for wv insn overlap, add the related wv insn test and mark it as xfail. And we will remove the xfail after we support the register overlap in GCC-15. b3b2799b872 RISC-V: Support one more overlap for wv instructions gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr112431-42.c: New test. Signed-off-by: Pan Li --- .../gcc.target/riscv/rvv/base/pr112431-42.c | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-42.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-42.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-42.c new file mode 100644 index 00000000000..fa5dac58a20 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-42.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ffast-math" } */ + +#include + +int64_t +reduc_plus_int (int *__restrict a, int n) +{ + int64_t r = 0; + for (int i = 0; i < n; ++i) + r += a[i]; + return r; +} + +double +reduc_plus_float (float *__restrict a, int n) +{ + double r = 0; + for (int i = 0; i < n; ++i) + r += a[i]; + return r; +} + +/* { dg-final { scan-assembler-not {vmv1r} { xfail riscv*-*-* } } } */ +/* { dg-final { scan-assembler-not {vmv2r} } } */ +/* { dg-final { scan-assembler-not {vmv4r} } } */ +/* { dg-final { scan-assembler-not {vmv8r} } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-times {vwadd\.wv} 1 } } */ +/* { dg-final { scan-assembler-times {vfwadd\.wv} 1 } } */