From patchwork Mon Apr 15 06:33:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fei Gao X-Patchwork-Id: 1923583 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4VHyCs5qBwz1yXv for ; Mon, 15 Apr 2024 16:38:00 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4507E3858CDB for ; Mon, 15 Apr 2024 06:37:58 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from azure-sdnproxy.icoremail.net (azure-sdnproxy.icoremail.net [207.46.229.174]) by sourceware.org (Postfix) with ESMTP id CB5E93858D34 for ; Mon, 15 Apr 2024 06:37:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CB5E93858D34 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org CB5E93858D34 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=207.46.229.174 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1713163062; cv=none; b=bToJuYqWMGzQ3zduc4uRGnJiKYPekmcReqHpNk8JORI9XqDIkPlCGhfTFzR0+8pXNnyuANX9E66FjkcBxiN18yQSz9aRDTwTDRe6bY7b7qq9ch98pI8qDvfgHq2jRCQ25Ut/WUxbfiiPSLMxyfjqBRMBUHb21VSD3529LRu6ZYg= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1713163062; c=relaxed/simple; bh=jv7y6CgcL9NMjZkRZZ45z5eiIBKgHR424ePW4jyW3Yw=; h=From:To:Subject:Date:Message-Id; b=R3L6uSD3QOrsAJ92001WBWN9trVHdczpEkg2ysDDxLSYK2pve8PjukGl9v5J0j+5LijmuylgdaL6UUUDXMUTY8X5ZSIEFPl5uoVRMsxNZdZruRwf9VcraPXVEsBpb0K0IlS/+VC6Vi7gPqxhvggqEr24OqN6Tvn3YFLLL0Gu7I0= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from localhost.localdomain (unknown [10.12.130.31]) by app2 (Coremail) with SMTP id TQJkCgAXKbveyhxm5Y0GAA--.28856S4; Mon, 15 Apr 2024 14:36:14 +0800 (CST) From: Fei Gao To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, jeffreyalaw@gmail.com, Fei Gao Subject: [PATCH] [RISC-V] optimize Zicond conditional select cases. Date: Mon, 15 Apr 2024 06:33:17 +0000 Message-Id: <20240415063317.29372-1-gaofei@eswincomputing.com> X-Mailer: git-send-email 2.17.1 X-CM-TRANSID: TQJkCgAXKbveyhxm5Y0GAA--.28856S4 X-Coremail-Antispam: 1UD129KBjvJXoW7Kr4kWw4rXr1Dury3Gw1fCrg_yoW8Kr1Upa ykK3yayFW8AFZxGw1SqF48Kw1Svwn3WryY9r97Ar18Aa15trZrXF4DKa17Zry3Ja1rXrnr urZrur4jvr1UKwUanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUk214x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc2xSY4AK6svPMxAI w28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr 4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxG rwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8Jw CI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2 z280aVCY1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjfUoOJ5UUUUU X-CM-SenderInfo: xjdrwv3l6h245lqf0zpsxwx03jof0z/ X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org When one of the two input operands is 0, ADD and IOR are functionally equivalent. ADD is slightly preferred over IOR because ADD has a higher likelihood of being implemented as a compressed instruction when compared to IOR. C.ADD uses the CR format with any of the 32 RVI registers availble, while C.OR uses the CA format with limit to just 8 of them. Conditional select, if zero case: rd = (rc == 0) ? rs1 : rs2 before patch: czero.nez rd, rs1, rc czero.eqz rtmp, rs2, rc or rd, rd, rtmp after patch: czero.eqz rd, rs1, rc czero.nez rtmp, rs2, rc add rd, rd, rtmp Same trick applies for the conditional select, if non-zero case: rd = (rc != 0) ? rs1 : rs2 riscv-gnu-toolchain regression tests have been passed with no new failure. --- gcc/config/riscv/riscv.cc | 2 +- .../gcc.target/riscv/zicond-prefer-add-to-or.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-prefer-add-to-or.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index e5f00806bb9..93c736549c9 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4709,7 +4709,7 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt) gen_rtx_IF_THEN_ELSE (mode, cond1, CONST0_RTX (mode), alt))); - riscv_emit_binary (IOR, dest, reg1, reg2); + riscv_emit_binary (PLUS, dest, reg1, reg2); return true; } } diff --git a/gcc/testsuite/gcc.target/riscv/zicond-prefer-add-to-or.c b/gcc/testsuite/gcc.target/riscv/zicond-prefer-add-to-or.c new file mode 100644 index 00000000000..f3f7beb0b5e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zicond-prefer-add-to-or.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicond -mabi=lp64d -mbranch-cost=4" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f -mbranch-cost=4" { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } {"-O0" "-Og" "-Os" "-Oz"} } */ + +long cond_select_if_zero(long a, long b, long c) { + return a == 0 ? c : b; +} + +long cond_select_if_non_zero(long a, long b, long c) { + return a != 0 ? c : b; +} + +/* { dg-final { scan-assembler-times {add\t} 2 } } */ +/* { dg-final { scan-assembler-not {or\t} } } */ +